# US 2026/0107856 A1 · Semiconductor packages and methods of forming the same

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- Number: US 2026/0107856 A1
- Document ID: US20260107856A1
- Status: Published application
- Kind: A1
- Application number: 19/046,429
- Filed: 2025-02-05
- Published: 2026-04-16
- Earliest claimed: 2024-10-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hung-Min Chang; Chien-Chang Lin; Hsuan-Cheng Kuo; Shih-Hui Wang; Tzu-Shiun Sheu
- Web page: https://patentgrep.com/patent/US20260107856A1

## CPC

- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/635: {Through-vias}
- H10W 76/60: Seals
- H10W 90/00: Package configurations
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 40/235: {attached to package parts}
- H10W 70/611: {for connecting multiple chips together}
- H10W 72/30: Die-attach connectors
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/10: Containers or parts thereof
- H10W 76/63: characterised by their shape or disposition, e.g. between cap and walls of a container
- H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a board substrate, an integrated circuit component and a ring structure. The integrated circuit component is bonded to the board substrate and includes at least one semiconductor die. The ring structure is disposed on the board substrate and encircles the integrated circuit component, wherein the ring structure includes a plurality of cavities around a boundary of the integrated circuit component.

## Claims

### Claim 1

A semiconductor package, comprising;
a board substrate;
an integrated circuit component, bonded to the board substrate and comprising at least one semiconductor die; and
a ring structure, disposed on the board substrate and encircling the integrated circuit component, wherein the ring structure comprises a plurality of cavities around a boundary of the integrated circuit component.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the cavities penetrate through the ring structure.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the cavities do not penetrate through the ring structure.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the cavities face the board substrate.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the cavities face away from the board substrate.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein some of the cavities face the board substrate, and some of the cavities face away from the board substrate.
The semiconductor package of claim 1, wherein a longitude direction of the cavities is perpendicular to a corresponding sidewall of the integrated circuit component.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein a longitude direction of the cavities is parallel to a corresponding sidewall of the integrated circuit component.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, further comprising a cover member disposed on the ring structure and the integrated circuit component.

### Claim 10

A semiconductor package, comprising;
a board substrate;
an integrated circuit component, bonded to the board substrate and comprising at least one semiconductor die;
a ring structure, disposed on the board substrate and encircling the integrated circuit component, wherein the ring structure comprises first portions and second portions thicker than the first portions; and
a cover member, disposed on the ring structure and the integrated circuit component.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein the first portions are in contact with the cover member.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, wherein the first portions are separated from the cover member.

### Claim 13 (depends on 10)

The semiconductor package of claim 10, wherein the second portions have inclined sidewalls.

### Claim 14 (depends on 10)

The semiconductor package of claim 10, wherein the second portions have substantially vertical sidewalls.

### Claim 15 (depends on 10)

The semiconductor package of claim 10, further comprising a passive device disposed on the board substrate corresponding to one of the first portions.

### Claim 16 (depends on 10)

The semiconductor package of claim 10, further comprising a discontinuous adhesive layer between the ring structure and the board substrate.

### Claim 17

A method of forming a semiconductor package, comprising:
bonding an integrated circuit component to a board substrate, wherein the integrated circuit component comprises at least one semiconductor die;
forming an underfill layer between the integrated circuit component and the board substrate; and
attaching a ring structure to the board substrate, wherein the ring structure encircles the integrated circuit component, and comprises a plurality of cavities around a boundary of the integrated circuit component.

### Claim 18 (depends on 17)

The method of claim 17, further comprising bonding a passive device to the board substrate before attach the ring structure to the board substrate, wherein the passive device corresponds to one of the cavities.

### Claim 19 (depends on 17)

The method of claim 17, wherein the cavities penetrating through the ring structure.

### Claim 20 (depends on 17)

The method of claim 17, wherein the cavities do not penetrate through the ring structure.
