Vertical multi-transistor device

A semiconductor package, comprising:

• a first transistor chip having a first side and a second side opposite the first side, wherein the first side comprises at least one source chip pad (S1) and at least one drain chip pad (D1);
• a second transistor chip having a first side and a second side opposite the first side, wherein the first side comprises at least one source chip pad (S2) and at least one drain chip pad (D2);
• and
• a chip carrier having a first main side and a second main side opposite the first main side, wherein the first main side of the chip carrier faces the first side of the first transistor chip and is attached to the at least one source chip pad and the at least one drain chip pad of the first transistor chip, and the second main side of the chip carrier faces the first side of the second transistor chip and is attached to the at least one source chip pad and the at least one drain chip pad of the second transistor chip;
• wherein the chip carrier is configured:
• to electrically connect the first transistor chip and the second transistor chip serially in a D1-S1-D2-S2 configuration, in a S1-D1-D2-S2 configuration, or in a D1-S1-S2-D2 configuration;
• and
• to be attached to an application board in an inclined orientation relative to the application board.