Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsJunbae KIM, Geunwoo KIM, Byoung-Gug MIN
Life of this patent
Estimating the term…
Abstract
A semiconductor package may include a package substrate including a plurality of upper pads, a semiconductor chip on the package substrate and electrically connected to at least one of the plurality of upper pads, a sealing layer covering at least a portion of the semiconductor chip and the package substrate, and a capacitor structure including a first conductive layer covering one side surface of the package substrate and a portion of the sealing layer, a second conductive layer covering another side surface of the package substrate and another portion of the sealing layer, and a dielectric layer being between the first conductive layer and the second conductive layer.
Claims20
A semiconductor package comprising:
- a package substrate including a plurality of upper pads;
- a semiconductor chip on the package substrate and electrically connected to at least one of the plurality of upper pads;
- a sealing layer configured to cover at least a portion of the semiconductor chip and the package substrate;
- and
- a capacitor structure including a first conductive layer configured to cover one side surface of the package substrate and a portion of the sealing layer, a second conductive layer configured to cover another side surface of the package substrate and another portion of the sealing layer, and a dielectric layer being between the first conductive layer and the second conductive layer.
A semiconductor package comprising:
- a package substrate including a plurality of upper pads;
- a semiconductor chip on the package substrate and electrically connected to at least one of the plurality of upper pads;
- a sealing layer configured to cover at least a portion of the semiconductor chip and the package substrate, the sealing layer including a connection structure electrically connected to a second conductive layer;
- and
- a capacitor structure including a first conductive layer configured to cover one side surface of the package substrate and a portion of the sealing layer, the second conductive layer configured to cover another side surface of the package substrate and another portion of the sealing layer, and a dielectric layer being between the first conductive layer and the second conductive layer.
A semiconductor package comprising:
- a package body including
- a package substrate including a first wiring layer and a second wiring layer,
- a semiconductor chip on the package substrate and electrically connected to the first wiring layer, and
- a sealing layer configured to cover at least a portion of the semiconductor chip and the package substrate;
- a capacitor structure including
- a first conductive layer in contact with one side surface of the package body,
- a second conductive layer in contact with another side surface and an upper surface of the package body, and
- a dielectric layer being between the first conductive layer and the second conductive layer;
- a conductive structure in contact with the second conductive layer of the capacitor structure;
- a base substrate including
- a first connection wiring line below the package body and the conductive structure and electrically connected to the first wiring layer,
- a second connection wiring line electrically connected to the second wiring layer, and
- a third connection wiring line electrically connected to the conductive structure;
- and
- a first connection bump, a second connection bump, and a third connection bump being below the base substrate and electrically connected to the first connection wiring line, the second connection wiring line, and the third connection wiring line, respectively.
Dependencies are inferred from the claim text.