# US 2026/0107802 A1 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0107802 A1 - Document ID: US20260107802A1 - Status: Published application - Kind: A1 - Application number: 19/214,327 - Filed: 2025-05-21 - Published: 2026-04-16 - Earliest claimed: 2024-10-10 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Eunkyeong PARK; SANG SUB SONG; SEOKBEOM YONG - Web page: https://patentgrep.com/patent/US20260107802A1 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/611: {for connecting multiple chips together} - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10D 80/30: the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/685: comprising multiple insulating layers - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor package may include a wiring substrate including a plurality of interconnection layers. The interconnection layers may include a first interconnection layer and a second interconnection layer on the first interconnection layer. The first interconnection layer may include first conductive lines, which include two first ground lines spaced apart from each other in a first direction and two first signal lines interposed therebetween and which extend lengthwise in a second direction perpendicular to the first direction. The second interconnection layer may include second conductive lines including a primary second signal line, which is adjacent to one of the two first signal lines in a third direction perpendicular to the first and second directions, and a primary second ground line, which is adjacent to another of the two first signal lines in the third direction. The second conductive lines may extend lengthwise in the second direction. ## Claims ### Claim 1 A semiconductor package, comprising: a wiring substrate including a plurality of interconnection layers, wherein the plurality of interconnection layers comprise: a first interconnection layer; and a second interconnection layer on the first interconnection layer, wherein the first interconnection layer comprises first conductive lines, which include two first ground lines spaced apart from each other in a first direction and two first signal lines interposed therebetween, and which extend lengthwise in a second direction perpendicular to the first direction, wherein the second interconnection layer comprises second conductive lines including a primary second signal line, which is adjacent to one of the two first signal lines in a third direction perpendicular to the first and second directions, and a primary second ground line, which is adjacent to another of the two first signal lines in the third direction, and wherein the second conductive lines extend lengthwise in the second direction. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the two first ground lines and the two first signal lines are adjacently arranged in the order of the first ground line, the first signal line, the first signal line, and the first ground line in the first direction. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the second conductive lines comprise two second ground lines including the primary second ground line and a secondary second ground line spaced apart from each other in the first direction, and the primary second signal line interposed therebetween, and wherein the primary second signal line is adjacent to the two second ground lines. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the second conductive lines comprise two second ground lines, including the primary second ground line and a secondary second ground line, and two second signal lines, including the primary second signal line and a secondary second signal line, interposed therebetween in the first direction, and wherein the two second signal lines are adjacent to each other. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the first conductive lines are arranged along a first arrangement pattern, wherein the second conductive lines are arranged along a second arrangement pattern, and wherein the first and second arrangement patterns are different from each other. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the first conductive lines are arranged along a first arrangement pattern, wherein the second conductive lines are arranged along a second arrangement pattern, wherein the first and second arrangement patterns are the same as each other, and wherein the second conductive lines comprise an arrangement pattern offset from the first conductive lines in the first direction. ### Claim 7 (depends on 6) The semiconductor package of claim 6, wherein the second conductive lines are offset from the first conductive lines by a distance that is given as a sum of a width of the first signal line in the first direction and a distance between the two first signal lines in the first direction. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein a distance between the first and second interconnection layers in the third direction is larger than a distance between the first signal lines in the first direction. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein a distance between a first ground line of the two first ground lines and a first signal line of the two first signal lines, which are adjacent to each other, is equal to a distance between the two first signal lines, which are adjacent to each other. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein a distance between a first ground line of the two first ground lines and a first signal line of the two first signal lines, which are adjacent to each other, is smaller than a distance between the two first signal lines, which are adjacent to each other. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein a width of the first ground line in the first direction is smaller than a width of the first signal line in the first direction. ### Claim 12 (depends on 10) The semiconductor package of claim 10, wherein a width of the first ground line in the first direction is larger than a width of the first signal line in the first direction. ### Claim 13 (depends on 1) The semiconductor package of claim 1, wherein the first interconnection layer further comprises first pads, which are spaced apart from each other in the first direction with the first conductive lines interposed therebetween, wherein the second interconnection layer further comprises second pads, which are spaced apart from each other in the first direction with the second conductive lines interposed therebetween, and wherein the semiconductor package further comprises vias directly connecting the first pads to the second pads. ### Claim 14 A semiconductor package, comprising: a wiring substrate including a plurality of interconnection layers, wherein the plurality of interconnection layers comprise: a first interconnection layer; and a second interconnection layer on the first interconnection layer, wherein the first interconnection layer comprises first pads, which are spaced apart from each other in a first direction, and first conductive lines, which are disposed between the first pads and are arranged in the first direction, wherein the second interconnection layer comprises second pads, which are spaced apart from each other in the first direction, and second conductive lines, which are disposed between the second pads and are arranged in the first direction, wherein each of the first and second conductive lines extends lengthwise in a second direction perpendicular to the first direction, wherein the first conductive lines comprise first ground lines and first signal lines arranged along a first arrangement pattern, wherein the second conductive lines comprise second ground lines and second signal lines arranged along a second arrangement pattern, wherein the first arrangement pattern is a pattern in which the first ground line, the first signal line, the first signal line, and the first ground line are repeatedly arranged in the first direction, and wherein a number of the second signal lines in the second interconnection layer is different from a number of the first signal lines in the first interconnection layer. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the second arrangement pattern is different from the first arrangement pattern, and wherein the second arrangement pattern is a pattern in which the second ground line, the second signal line, and the second ground line are repeatedly arranged in the first direction. ### Claim 16 (depends on 14) The semiconductor package of claim 14, wherein the second arrangement pattern is a pattern in which the second ground line, the second signal line, the second signal line, and the second ground line are repeatedly arranged in the first direction. ### Claim 17 (depends on 14) The semiconductor package of claim 14, wherein the wiring substrate further comprises a third interconnection layer and a fourth interconnection layer on the second interconnection layer, wherein the fourth interconnection layer is spaced apart from the second interconnection layer with the third interconnection layer interposed therebetween, and wherein the third interconnection layer comprises third conductive lines arranged along the first arrangement pattern. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein the fourth interconnection layer is arranged along the second arrangement pattern. ### Claim 19 (depends on 17) The semiconductor package of claim 17, wherein the fourth interconnection layer is arranged along a third arrangement pattern different from the first and second arrangement patterns. ### Claim 20 A semiconductor package, comprising: a package substrate; an interposer on the package substrate; and a first semiconductor chip and a second semiconductor chip on the interposer, wherein the interposer comprises a wiring substrate including a plurality of interconnection layers, wherein the plurality of interconnection layers comprise: a first interconnection layer; and a second interconnection layer on the first interconnection layer, wherein the first interconnection layer comprises first conductive lines, which include two first ground lines spaced apart from each other in a first direction and two first signal lines interposed therebetween and which extend lengthwise in a second direction perpendicular to the first direction, wherein the second interconnection layer comprises second conductive lines including a second signal line, which is adjacent to one of the two first signal lines in a third direction perpendicular to the first and second directions, and a second ground line, which is adjacent to another of the two first signal lines in the third direction, wherein the second conductive lines extend lengthwise in the second direction, and wherein the first and second semiconductor chips are spaced apart from each other in the second direction.