# US 2026/0107800 A1 · Semiconductor package with integrated ground lines and signal lines

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- Number: US 2026/0107800 A1
- Document ID: US20260107800A1
- Status: Published application
- Kind: A1
- Application number: 19/089,703
- Filed: 2025-03-25
- Published: 2026-04-16
- Earliest claimed: 2024-10-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Minjong WANG; Keunyoung LEE; Eunhye LEE
- Web page: https://patentgrep.com/patent/US20260107800A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10D 80/30: the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips
- H10W 70/611: {for connecting multiple chips together}
- H10W 90/00: Package configurations
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 44/203: {Electrical connections}
- H10W 44/206: {Wires}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/7295: {on the rear surface of insulating package substrates, interposers or RDLs, for connection outside of the package, e.g. ball grid array [BGA] bumps}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor package includes: a package substrate including a first surface and a second surface opposite each other; at least one signal pad arranged in a first direction, at least one ground pad spaced apart from the at least one signal pad in a second direction; and a semiconductor chip on the package substrate, the semiconductor chip including at least one first pad and at least one second pad. The package substrate includes at least one signal line connected to the at least one signal pad; and a at least one ground line connected to the at least one ground pad, in which the at least one ground line extends between the at least one signal pad and the at least one ground pad in the first direction, and in which the at least one second pad is connected to the at least one ground pad through a second bonding wire.

## Claims

### Claim 1

A semiconductor package comprising:
a package substrate comprising a first surface and a second surface opposite to each other;
at least one signal pad on the first surface of the package substrate, the first direction being a direction parallel to the first surface of the package substrate;
at least one ground pad on the first surface of the package substrate and spaced apart from the signal pad in a second direction, the second direction being a direction parallel to the first surface of the package substrate and intersecting the first direction; and
a semiconductor chip on the package substrate, the semiconductor chip comprising at least one first pad and at least one second pad,
wherein the package substrate further comprises:
at least one signal line connected to the at least one signal pad; and
at least one ground line connected to the at least one ground pad,
wherein the at least one ground line extends between the at least one signal pad and the at least one ground pad in the first direction,
wherein the at least one first pad is connected to the at least one signal pad through a first bonding wire, and
wherein the at least one second pad is connected to the at least one ground pad through a second bonding wire.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the at least one ground line extends between the at least one signal lines.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein a signal pad among the at least one signal pad and a ground pad, adjacent to the signal pad, among the at least one ground pad are spaced apart from each other by a first distance in the second direction.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein at the least one ground line has a first width in the second direction, and
wherein the first distance is greater than the first width.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the first distance is greater than the first width and is smaller than or equal to 10 times the first width.

### Claim 6 (depends on 4)

The semiconductor package of claim 4, wherein the first width is 10 μm to 20 μm, and
wherein the first distance is greater than 10 μm and is less than or equal to 200 μm.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the semiconductor chip is spaced apart from the at least one signal pad and the at least one ground pad in the second direction.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the semiconductor chip is spaced apart from the at least one signal line and the at least one ground line in the second direction.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the at least one ground line comprises a plurality of ground lines which comprise:
at least one first ground line pattern extending in the second direction and spaced apart from each other in the first direction with the at least one signal line interposed therebetween;
a second ground line pattern extending between the at least one signal pad and the at least one ground pad in the first direction and connected to the at least one first ground line pattern; and
a third ground line pattern extending from the second ground line pattern in the second direction and connected to a corresponding ground pad among the at least one ground pad.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein each of the first bonding wire and the second bonding wire comprises at least one of copper, gold, aluminum, and an alloy thereof.

### Claim 11

A semiconductor package comprising:
a package substrate comprising a first surface and a second surface opposite to each other;
a first semiconductor chip on the first surface of the package substrate;
a plurality of memory chips on the first surface of the package substrate;
a plurality of first signal pads on the first surface of the package substrate and arranged in a first direction, the first direction being a direction parallel to the first surface of the package substrate;
a plurality of ground pads on the first surface of the package substrate and arranged in the first direction and spaced apart from the plurality of first signal pads in a second direction, respectively, the second direction being a direction parallel to the first surface of the package substrate and intersecting the first direction;
a plurality of second signal pads on the first surface of the package substrate and arranged in the first direction;
a plurality of first bonding wires connecting the plurality of first signal pads and the first semiconductor chip, respectively;
a plurality of second bonding wires connecting the plurality of ground pads and the first semiconductor chip, respectively; and
a plurality of third bonding wires connecting the plurality of second signal pads and the plurality of memory chips, respectively,
wherein the plurality of first signal pads are disposed between the plurality of ground pads and the plurality of second signal pads, respectively,
wherein the package substrate comprises:
a plurality of signal lines connecting the plurality of first signal pads and the plurality of second signal pads, respectively; and
a plurality of ground lines connected to the plurality of ground pads, respectively, and
wherein at least one of the plurality of ground lines extends between the plurality of ground pads and the plurality of first signal pads in the first direction, respectively.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein the plurality of first signal pads and the plurality of ground pads are spaced apart from each other by a first distance in the second direction.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein each of the plurality of ground lines has a first width in the second direction, and
wherein the first distance is greater than the first width and less than or equal to 10 times the first width.

### Claim 14 (depends on 11)

The semiconductor package of claim 11, wherein the first semiconductor chip is spaced apart from the plurality of first signal pads, the plurality of second signal pads, and the plurality of ground pads in the second direction.

### Claim 15 (depends on 11)

The semiconductor package of claim 11, wherein the plurality of ground lines comprise:
a plurality of first ground line patterns extending in the second direction and spaced apart from each other in the first direction with at least one signal line of the plurality of signal lines interposed therebetween;
a second ground line pattern extending between the plurality of first signal pads and the plurality of ground pads in the first direction and connected to the plurality of first ground line patterns; and
a third ground line pattern extending from the second ground line pattern in the second direction and connected to a corresponding ground pad of the plurality of ground pads.

### Claim 16 (depends on 11)

The semiconductor package of claim 11, wherein the first semiconductor chip comprises a logic chip.

### Claim 17

A semiconductor package comprising:
a package substrate comprising a first surface and a second surface opposite to each other;
a first semiconductor chip on the first surface of the package substrate;
a plurality of memory chips on the first surface of the package substrate and stacked on the first semiconductor chip;
a plurality of first signal pads arranged in a first direction on the first surface of the package substrate, the first direction being a direction parallel to the first surface of the package substrate;
a plurality of ground pads arranged in the first direction on the first surface of the package substrate and spaced apart from the plurality of first signal pads, respectively, in a second direction, the second direction being a direction parallel to the first surface of the package substrate and intersecting the first direction;
a plurality of second signal pads on the first surface of the package substrate and arranged in the first direction;
a plurality of first bonding wires connecting the plurality of first signal pads and the first semiconductor chip, respectively;
a plurality of second bonding wires connecting the plurality of ground pads and the first semiconductor chip, respectively; and
a plurality of third bonding wires connecting the plurality of second signal pads and the plurality of memory chips, respectively,
wherein the plurality of first signal pads are between the plurality of ground pads and the plurality of second signal pads, respectively,
wherein the package substrate comprises:
a plurality of signal lines connecting the plurality of first signal pads and the plurality of second signal pads, respectively; and
a plurality of ground lines connected to the plurality of ground pads, and
wherein at least one of the plurality of ground lines extends between the plurality of ground pads and the plurality of first signal pads in the first direction, respectively.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein the plurality of first signal pads are respectively spaced apart from the plurality of ground pads by a first distance in the second direction.

### Claim 19 (depends on 17)

The semiconductor package of claim 17, wherein the plurality of ground lines comprise:
a plurality of first ground line patterns extending in the second direction and spaced apart in the first direction with at least one of the plurality of signal lines interposed therebetween;
a second ground line pattern extending between the plurality of first signal pads and the plurality of ground pads, respectively, in the first direction and connected to the plurality of first ground line patterns, respectively; and
a third ground line pattern extending from the second ground line pattern in the second direction and connected to a corresponding ground pad among the plurality of ground pads.

### Claim 20 (depends on 17)

The semiconductor package of claim 17, wherein each of the plurality of first bonding wires and the plurality of second bonding wires comprises at least one of copper, gold, aluminum, and an alloy thereof.