# US 2026/0107792 A1 · Semiconductor module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0107792 A1 - Document ID: US20260107792A1 - Status: Published application - Kind: A1 - Application number: 19/245,365 - Filed: 2025-06-22 - Published: 2026-04-16 - Earliest claimed: 2024-07-31 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Ryoga KIGUCHI - Web page: https://patentgrep.com/patent/US20260107792A1 ## CPC - H10W 70/611: {for connecting multiple chips together} - G01K 1/026: {arrangements for monitoring a plurality of temperatures, e.g. by multiplexing} - H10W 40/50: Arrangements for sensing temperature - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/652: Cross-sectional shapes - H10W 70/654: Top-view layouts - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/20: Configurations of stacked chips - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00) ## Abstract Provided is a semiconductor module including a stacked substrate in which a plurality of wiring layers are stacked, and a plurality of semiconductor devices mounted on a first surface of the stacked substrate, wherein the plurality of wiring layers have a first wiring layer having a high-potential wiring to which a high potential is applied, a second wiring layer having a low-potential wiring to which a low potential is applied, and a third wiring layer having a connection wiring which connects the plurality of semiconductor devices mounted on the first surface of the stacked substrate to each other, and the high-potential wiring and the low-potential wiring are at least partially overlapped with each other in a stack direction. ## Claims ### Claim 1 A semiconductor module, comprising: a stacked substrate in which a plurality of wiring layers are stacked; and a plurality of semiconductor devices mounted on a first surface of the stacked substrate, wherein the plurality of wiring layers have a first wiring layer having a high-potential wiring to which a high potential is applied, a second wiring layer having a low-potential wiring to which a low potential is applied, and a third wiring layer having a connection wiring which connects the plurality of semiconductor devices mounted on the first surface of the stacked substrate to each other, and the high-potential wiring and the low-potential wiring are at least partially overlapped with each other in a stack direction. ### Claim 2 (depends on 1) The semiconductor module according to claim 1, comprising at least one temperature sensor which is arranged on a side with a second surface of the stacked substrate and detects a temperature of at least one of the plurality of semiconductor devices. ### Claim 3 (depends on 2) The semiconductor module according to claim 2, comprising a plurality of temperature sensors, each temperature sensor being identical to the temperature sensor, which are arranged on the side with the second surface of the stacked substrate and each detects a temperature of the plurality of semiconductor devices. ### Claim 4 (depends on 2) The semiconductor module according to claim 2, wherein the at least one temperature sensor is arranged so as to be overlapped with the at least one of the plurality of semiconductor devices in the stack direction. ### Claim 5 (depends on 2) The semiconductor module according to claim 2, wherein the stacked substrate includes a conductor of which one end is connected to a main electrode plate of at least one semiconductor device among the plurality of semiconductor devices, and which extends to the third wiring layer. ### Claim 6 (depends on 5) The semiconductor module according to claim 5, wherein the conductor is formed in a non-penetrating way in the stacked substrate. ### Claim 7 (depends on 5) The semiconductor module according to claim 5, wherein the temperature sensor corresponding to at least one semiconductor device among the plurality of semiconductor devices is mounted at a position which overlaps with the conductor connected to the semiconductor device in the stack direction. ### Claim 8 (depends on 2) The semiconductor module according to claim 2, wherein the stacked substrate has a temperature detection conductor, which is non-penetrating, between the at least one temperature sensor and the at least one of the plurality of semiconductor devices in the stack direction. ### Claim 9 (depends on 8) The semiconductor module according to claim 8, wherein the temperature detection conductor extends from a wiring layer, among the plurality of wiring layers, which is connected to the at least one of the plurality of semiconductor devices toward the second surface of the stacked substrate in the stack direction. ### Claim 10 (depends on 2) The semiconductor module according to claim 2, comprising at least one control device which is arranged on the second surface of the stacked substrate, and controls the at least one semiconductor device, wherein the control device controls the at least one semiconductor device according to the temperature of the at least one semiconductor device detected by the temperature sensor. ### Claim 11 (depends on 10) The semiconductor module according to claim 10, wherein the control device acquires a lifetime of the at least one semiconductor device which is estimated from the temperature detected by the temperature sensor, and controls the at least one semiconductor device according to the lifetime of the at least one semiconductor device. ### Claim 12 (depends on 10) The semiconductor module according to claim 10, wherein a plurality of control devices, each control device being identical to the control device, are arranged on the second surface of the stacked substrate, and respectively control the plurality of semiconductor devices. ### Claim 13 (depends on 1) The semiconductor module according to claim 1, wherein each of the plurality of semiconductor devices is provided with a first main electrode plate, a second main electrode plate, and a control electrode plate on one surface thereof, and has a switching element in which a first main electrode is connected to the first main electrode plate, a second main electrode is connected to the second main electrode plate, and a control electrode is connected to the control electrode plate, and the connection wiring of the third wiring layer connects the first main electrode plate of a first semiconductor device among the plurality of semiconductor devices, and the second main electrode plate of a second semiconductor device among the plurality of semiconductor devices to each other. ### Claim 14 (depends on 13) The semiconductor module according to claim 13, wherein the first semiconductor device is mounted, on the first surface of the stacked substrate, such that the first main electrode plate is closer to the second semiconductor device than the second main electrode plate, and the second semiconductor device is mounted, on the first surface of the stacked substrate, such that the second main electrode plate is closer to the first semiconductor device than the first main electrode plate. ### Claim 15 (depends on 1) The semiconductor module according to claim 1, wherein the high-potential wiring and the low-potential wiring are at least partially overlapped with the connection wiring in the stack direction. ### Claim 16 (depends on 1) The semiconductor module according to claim 1, wherein the plurality of wiring layers further have a fourth wiring layer having an output wiring which connects the plurality of semiconductor devices to an output terminal formed on a second surface of the stacked substrate. ### Claim 17 (depends on 16) The semiconductor module according to claim 16, wherein the high-potential wiring and the low-potential wiring are at least partially overlapped with the output wiring in the stack direction. ### Claim 18 (depends on 1) The semiconductor module according to claim 1, comprising at least one snubber capacitor which is arranged on a second surface of the stacked substrate between a positive terminal connected to the high-potential wiring and a negative terminal connected to the low-potential wiring.