# US 2026/0107786 A1 · Semiconductor packages with wettable flanks and related methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0107786 A1 - Document ID: US20260107786A1 - Status: Published application - Kind: A1 - Application number: 19/420,083 - Filed: 2025-12-15 - Published: 2026-04-16 - Earliest claimed: 2023-02-07 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Hui Min LER; Swee Har KHOR; Ziming CHANG; Kok Yang LAU; Heng Giap ONG - Web page: https://patentgrep.com/patent/US20260107786A1 ## CPC - H10W 70/457: {of metallic layers on leadframes} - H10W 70/04: of leadframes - H10W 74/014: {using batch processing} - H10W 72/0198: {batch processes} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Implementations of a method of providing wettable flanks on leads of a semiconductor package may include applying mold compound around a plurality of leads included in a leadframe; electroplating exposed portions of the plurality of leads; cutting at least one lead of the plurality of leads to expose a flank of the least one lead; applying an electrically conductive layer over the plurality of leads; electroplating the flank of the at least one lead to render the flank wettable; removing the electrically conductive layer from the plurality of leads; and singulating to form a semiconductor package. ## Claims ### Claim 1 A method of providing a wettable flank on a lead of a semiconductor package, the method comprising: applying an electrically conductive layer over a plurality of leads comprised in a leadframe, wherein at least one lead of the plurality of leads has a flank exposed; electroplating the flank of the at least one lead to render the flank wettable; removing the electrically conductive layer from the plurality of leads; and singulating the leadframe, after removing the electrically conductive layer, to singulate a semiconductor package. ### Claim 2 (depends on 1) The method of claim 1, wherein the electrically conductive layer is an electrically conductive tape. ### Claim 3 (depends on 2) The method of claim 2, wherein the electrically conductive tape covers the entire leadframe. ### Claim 4 (depends on 2) The method of claim 2, wherein the electrically conductive tape covers only a portion of a single side of the semiconductor package. ### Claim 5 (depends on 1) The method of claim 1, wherein an electroplated die flag of the leadframe is exposed when the electrically conductive layer is coupled over the at least one lead. ### Claim 6 (depends on 1) The method of claim 1, wherein electroplating the flank of the at least one lead further comprises rendering the flank wettable by reaching a plating thickness greater than 2 microns. ### Claim 7 A method of providing wettable flanks on leads of a plurality of semiconductor packages, the method comprising: providing a leadframe panel comprising a plurality of semiconductor packages, each semiconductor package having a plurality of leads and an exposed flank on at least one lead; applying an electrically conductive layer over leadframe panel; electroplating each exposed flank to render each exposed flank wettable; removing the electrically conductive layer; and singulating the leadframe panel after removing the electrically conductive layer to singulate the plurality of semiconductor packages. ### Claim 8 (depends on 7) The method of claim 7, wherein the electrically conductive layer is an electrically conductive tape. ### Claim 9 (depends on 8) The method of claim 8, wherein the electrically conductive tape covers the entire leadframe panel. ### Claim 10 (depends on 8) The method of claim 8, wherein the electrically conductive tape covers only a portion of a single side of each semiconductor package. ### Claim 11 (depends on 7) The method of claim 7, wherein the electrically conductive layer electrically couples with the at least one lead of each semiconductor package. ### Claim 12 (depends on 7) The method of claim 7, wherein electroplating each exposed flank of the at least one lead of each semiconductor package further comprises rendering each exposed flank wettable by reaching a plating thickness greater than 2 microns. ### Claim 13 (depends on 7) The method of claim 7, wherein an electroplated die flag of the leadframe panel is exposed when the electrically conductive layer is coupled over the leadframe panel. ### Claim 14 A method of providing a wettable flank on a lead of a semiconductor package, the method comprising: applying an electrically conductive layer over a plurality of leads comprised in a leadframe panel, wherein at least one lead of the plurality of leads has a flank exposed; coupling a jig over the plurality of leads, the jig providing an electrical connection to the at least one lead using a pogo pin; electroplating the at least one lead to render the flank wettable; removing the jig from the plurality of leads; and singulating the leadframe panel to singulate the semiconductor package. ### Claim 15 (depends on 14) The method of claim 14, wherein the jig is sized to contact multiple leads each having a flank exposed. ### Claim 16 (depends on 14) The method of claim 14, wherein the jig comprises electrically nonconductive material that forms a frame around each semiconductor package of the leadframe panel. ### Claim 17 (depends on 16) The method of claim 16, wherein multiple leads of the plurality of leads each has a flank exposed, wherein the electrically nonconductive material comprises electrical routing that electrically couples each lead of the multiple leads together. ### Claim 18 (depends on 14) The method of claim 14, wherein electroplating the at least one lead to render the flank wettable further comprises rendering the flank wettable by reaching a plating thickness greater than 2 microns. ### Claim 19 (depends on 14) The method of claim 14, wherein the pogo pin is spring loaded to apply a bias force to the at least one lead. ### Claim 20 (depends on 14) The method of claim 14, wherein the jig comprises a plurality of windows therethrough, each window sized to correspond with a size of each semiconductor package of the leadframe panel.