# US 2026/0107772 A1 · Semiconductor package assembly with direct water cooling system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0107772 A1 - Document ID: US20260107772A1 - Status: Published application - Kind: A1 - Application number: 19/357,090 - Filed: 2025-10-14 - Published: 2026-04-16 - Earliest claimed: 2024-10-14 - Assignees: STATS ChipPAC Pte. Ltd. - Applicants: STATS ChipPAC Pte. Ltd. - Inventors: JiSeon LEE; HeeSoo LEE - Web page: https://patentgrep.com/patent/US20260107772A1 ## CPC - H10W 40/40: involving heat exchange by flowing fluids - H10W 40/47: by flowing liquids, e.g. forced water cooling - H10W 70/611: {for connecting multiple chips together} - H10W 74/01: Manufacture or treatment - H10W 90/00: Package configurations - H10W 90/20: Configurations of stacked chips - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/7295: {on the rear surface of insulating package substrates, interposers or RDLs, for connection outside of the package, e.g. ball grid array [BGA] bumps} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package assembly, comprising: a first semiconductor package having at least one first electronic component exposed from its front surface; a second semiconductor package stacked on the first semiconductor package and having at least one second electronic component exposed from its front surface, wherein the first and second semiconductor packages define therebetween a first fluidic channel; and a lid stacked on the second semiconductor package; wherein the lid and the second semiconductor packages define therebetween a second fluidic channel to which the at least one second electronic component is exposed; wherein the second semiconductor package has openings passing therethrough to fluidly connect the first fluidic channel with the second fluidic channel, such that a coolant is capable of flowing within the first and second fluidic channels to dissipate heat generated by electronic components out of the semiconductor package assembly. ## Claims ### Claim 1 A semiconductor package assembly, comprising: a first semiconductor package having at least one first electronic component exposed from its front surface; a second semiconductor package stacked on the first semiconductor package and having at least one second electronic component exposed from its front surface, wherein the first and second semiconductor packages define therebetween a first fluidic channel to which the at least one first electronic component is exposed; and a lid stacked on and covering the second semiconductor package; wherein the lid and the second semiconductor packages define therebetween a second fluidic channel to which the at least one second electronic component is exposed; wherein the second semiconductor package has openings passing therethrough to fluidly connect the first fluidic channel with the second fluidic channel, such that a coolant is capable of flowing within the first and second fluidic channels to dissipate heat generated by the at least one first electronic component and the at least one second electronic component out of the semiconductor package assembly. ### Claim 2 (depends on 1) The semiconductor package assembly of claim 1, further comprising: a set of connection structures mounted between the first and second semiconductor packages and electrically connecting the first and second semiconductor packages with each other; wherein the set of connection structures are so formed that the first and second semiconductor packages are spaced apart from each other to form the first fluidic channel. ### Claim 3 (depends on 2) The semiconductor package assembly of claim 2, wherein the first semiconductor package comprises a first substrate where the at least one first electronic component is mounted, and wherein the set of connection structures are mounted on and electrically connected with the first substrate. ### Claim 4 (depends on 2) The semiconductor package assembly of claim 2, wherein the first semiconductor package has a fluid region where the first fluidic channel is formed and a non-fluid region where the set of connection structures is mounted, and wherein the semiconductor package assembly further comprises a sealing ring disposed between the first and second semiconductor packages and for enclosing the fluid region and separating the fluid region from the non-fluid region. ### Claim 5 (depends on 2) The semiconductor package assembly of claim 2, wherein the second semiconductor package comprises a second substrate where the at least one second electronic component is mounted, and wherein the set of connection structures are electrically connected with the second substrate. ### Claim 6 (depends on 1) The semiconductor package assembly of claim 1, further comprising: an adhesive layer formed between the second semiconductor package and the lid. ### Claim 7 (depends on 2) The semiconductor package assembly of claim 2, wherein the lid comprises a support portion which is connected to the second semiconductor package via the adhesive layer, and a fluid portion which is spaced apart from the second semiconductor package to form the second fluidic channel. ### Claim 8 (depends on 7) The semiconductor package assembly of claim 7, wherein the lid has a thinner thickness in the fluid portion than in the support portion. ### Claim 9 (depends on 1) The semiconductor package assembly of claim 1, wherein the lid comprises an inlet and an outlet passing therethrough and in fluid communication with the second fluidic channel, wherein the inlet is configured for receiving the coolant and the outlet is configured for outputting the coolant. ### Claim 10 (depends on 1) The semiconductor package assembly of claim 1, further comprising: a pump in fluid communication with the first and second fluid channels through a cooling pipe to circulate the coolant within the first and second fluid channels; and a radiator in fluid communication with the pump to cool the coolant which is out of the semiconductor package assembly. ### Claim 11 (depends on 10) The semiconductor package assembly of claim 10, further comprises: two valves mounted in the cooling pipe to regulate the flow of the coolant within the first and second fluid channels. ### Claim 12 (depends on 1) The semiconductor package assembly of claim 1, further comprising: at least a third semiconductor package mounted between the first and second semiconductor packages, wherein the first semiconductor package and the third semiconductor package define therebetween at least a fluidic channel to which the at least one first electronic component is exposed. ### Claim 13 A method for forming a semiconductor package assembly, comprising: providing a first semiconductor package, wherein the first semiconductor package has at least one first electronic component exposed from its front surface; mounting a second semiconductor package on the first semiconductor package to form a first fluidic channel between the first and second semiconductor packages, wherein the at least one first electronic component is exposed to the first fluid channel, and wherein the second semiconductor package comprises at least one second electronic component exposed from its front surface and openings passing therethrough; and stacking a lid on the second semiconductor package to cover the second semiconductor package and form a second fluidic channel between the second semiconductor package and the lid and in fluid connection with the first fluid channel, wherein the at least one second electronic component is exposed to the second fluidic channel. ### Claim 14 (depends on 13) The method of claim 13, wherein before the step of mounting a second semiconductor package on the first semiconductor package, the method further comprises: forming a first set of solder bumps on a first substrate of the first semiconductor package; forming a first encapsulant layer on the first substrate to encapsulate the at least one first electronic component and the first set of solder bumps; removing a portion of the first encapsulant layer to expose respective top surfaces of the at least one first electronic component and the first set of solder bumps; forming a second set of solder bumps on a second substrate of the second semiconductor package, wherein the second set of solder bumps are on opposite sides of the second substrate; and connecting and reflowing the first and second set of solder bumps to form a set of connection structures between the first and second semiconductor packages, wherein the first and second semiconductor packages are spaced apart from each other by the set of connection structures to form the first fluidic channel. ### Claim 15 (depends on 13) The method of claim 13, wherein before the step of mounting a second semiconductor package on the first semiconductor package, the method further comprises: forming a first set of solder bumps on a first substrate of the first semiconductor package; forming a first encapsulant layer on the first substrate to encapsulate the at least one first electronic component and the first set of solder bumps, wherein respective top surfaces of the at least one first electronic component is exposed from the first encapsulant layer; removing a portion of the first encapsulant layer to expose the first set of solder bumps; forming a second set of solder bumps on a second substrate of the second semiconductor package, wherein the second set of solder bumps are on opposite sides of the second substrate; and connecting and reflowing the first and second set of solder bumps to form a set of connection structures between the first and second semiconductor packages, wherein the first and second semiconductor packages are spaced apart from each other by the set of connection structures to form the first fluidic channel. ### Claim 16 (depends on 14) The method of claim 14, wherein before the step of forming a second set of solder bumps on a second substrate of the second semiconductor package, the method further comprises forming a sealing ring between the first and second semiconductor packages; and forming a sealing ring on the second substrate which is at the same side as the second set of solder bumps to separate the openings and the second set of solder bumps from each other. ### Claim 17 (depends on 13) The method of claim 13, wherein the step of stacking a lid on the second semiconductor package further comprises: forming an adhesive layer on a bottom surface of the lid; and attaching the lid onto the second semiconductor package via the adhesive layer. ### Claim 18 (depends on 13) The method of claim 13, further comprising: coupling a pump in fluid communication with the first and second fluid channels through a cooling pipe to circulate the coolant within the first and second fluid channels; and coupling a radiator with the pump to cool the coolant fluid. ### Claim 19 (depends on 13) The method of claim 13, further comprises: mounting two valves in the cooling pipe to regulate the flow of the coolant within the first and second fluid channels. ### Claim 20 (depends on 13) The method of claim 13, further comprising: mounting at least a third semiconductor package between the first and second semiconductor packages, wherein defining at least a fluidic channel between the first and at least a third semiconductor packages with at least one first electronic component exposed in it.