# US 2026/0107770 A1 · Semiconductor package

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- Number: US 2026/0107770 A1
- Document ID: US20260107770A1
- Status: Published application
- Kind: A1
- Application number: 19/209,991
- Filed: 2025-05-16
- Published: 2026-04-16
- Earliest claimed: 2024-10-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Eunbeom Jeon; Sangwoo Park
- Web page: https://patentgrep.com/patent/US20260107770A1

## CPC

- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 40/778: {in encapsulations}
- H10W 74/114: {by a substrate and the encapsulations}
- H05K 1/181: associated with surface mounted components
- H05K 2201/10515: Stacked components
- H10W 72/0198: {batch processes}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/965: {Providing thermal transfer}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/10: characterised by their shape or disposition
- H10W 90/00: Package configurations
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A semiconductor package according to an embodiment of the present disclosure includes: a substrate; a semiconductor chip on the substrate and electrically connected to the substrate; at least one heat dissipation wire connected to the semiconductor chip; and an encapsulant on at least a portion of each of the semiconductor chip and the heat dissipation wire. The heat dissipation wire is exposed to one side surface of side surfaces of the encapsulant.

## Claims

### Claim 1

A semiconductor package comprising:
a substrate;
a semiconductor chip on the substrate and electrically connected to the substrate;
at least one heat dissipation wire connected to the semiconductor chip; and
an encapsulant on at least a portion of each of the semiconductor chip and the heat dissipation wire,
wherein the heat dissipation wire is exposed to one side surface of side surfaces of the encapsulant.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the side surfaces of the encapsulant comprise a first side surface and a second side surface facing each other and a third side surface and a fourth side surface connecting the first side surface and the second side surface and facing each other, and wherein the heat dissipation wire comprises a first heat dissipation wire penetrating the first side surface of the encapsulant and a second heat dissipation wire penetrating the second side surface of the encapsulant.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein a distance between each of the first side surface and the second side surface and the semiconductor chip is less than a distance between each of the third side surface and the fourth side surface and the semiconductor chip.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, wherein the heat dissipation wire further comprises a third heat dissipation wire penetrating the third side surface of the encapsulant and a fourth heat dissipation wire penetrating the fourth side surface of the encapsulant.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising at least one bonding wire electrically connecting the semiconductor chip and the substrate.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein a diameter of the heat dissipation wire is greater than or equal to a diameter of the bonding wire.

### Claim 7 (depends on 5)

The semiconductor package of claim 5, wherein the semiconductor chip comprises a connection pad and a heat dissipation pad on a first surface, the bonding wire electrically connected to the connection pad, and the heat dissipation wire connected to the heat dissipation pad.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein a second surface opposite the first surface of the semiconductor chip faces the substrate.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, further comprising an adhesive member between the semiconductor chip and the substrate.

### Claim 10

A semiconductor package comprising:
a substrate;
a plurality of semiconductor chips on the substrate;
bonding wires electrically connecting each of the plurality of semiconductor chips to the substrate;
at least one heat dissipation wire connected to at least one of the plurality of semiconductor chips; and
an encapsulant on at least a portion of each of the plurality of semiconductor chips, the bonding wires, and the heat dissipation wire,
wherein the heat dissipation wire is exposed to one side surface of side surfaces of the encapsulant.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein the heat dissipation wire comprises a heat dissipation wire connected to an uppermost semiconductor chip among the plurality of semiconductor chips.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, wherein the side surfaces of the encapsulant comprise a first side surface and a second side surface facing each other and a third side surface and a fourth side surface connecting the first side surface and the second side surface and facing each other, the heat dissipation wire comprising a first heat dissipation wire penetrating the first side surface of the encapsulant and a second heat dissipation wire penetrating the second side surface of the encapsulant, the bonding wires comprising a first bonding wire electrically connected to the substrate and between the first side surface of the encapsulant and the plurality of semiconductor chips and a second bonding wire electrically connected to the substrate and between the second side surface of the encapsulant and the plurality of semiconductor chips.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the heat dissipation wire further comprises a third heat dissipation wire penetrating the third side surface of the encapsulant and a fourth heat dissipation wire penetrating the fourth side surface of the encapsulant.

### Claim 14 (depends on 10)

The semiconductor package of claim 10, wherein the side surfaces of the encapsulant comprise a first side surface and a second side surface facing each other and a third side surface and a fourth side surface connecting the first side surface and the second side surface and facing each other, the heat dissipation wire comprising a first heat dissipation wire penetrating the third side surface of the encapsulant and a second heat dissipation wire penetrating the fourth side surface of the encapsulant, and the bonding wires comprising a first bonding wire electrically connected to the substrate and between the first side surface of the encapsulant and the plurality of semiconductor chips and a second bonding wire electrically connected to the substrate and between the second side surface of the encapsulant and the plurality of semiconductor chips.

### Claim 15 (depends on 10)

The semiconductor package of claim 10, wherein the bonding wires comprise a bonding wire electrically connecting one semiconductor chip of the plurality of semiconductor chips to another semiconductor chip of the plurality of semiconductor chips.

### Claim 16 (depends on 10)

The semiconductor package of claim 10, wherein each of the bonding wires extends from a corresponding semiconductor chip of the plurality of semiconductor chips to the substrate.

### Claim 17

A semiconductor package comprising:
a substrate;
a first semiconductor chip on the substrate;
a second semiconductor chip spaced apart from the first semiconductor chip and on the substrate;
first bonding wires that electrically connect the first semiconductor chip and the substrate;
second bonding wires that electrically connect the second semiconductor chip and the substrate;
a first heat dissipation wire connected to the first semiconductor chip;
a second heat dissipation wire connected to the second semiconductor chip; and
an encapsulant on at least a portion of each of the first and second semiconductor chips, the first bonding wires, the second bonding wires, the first heat dissipation wire, and the second heat dissipation wire,
wherein each of the first heat dissipation wire and the second heat dissipation wire is exposed to one side surface of side surfaces of the encapsulant.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein the side surfaces of the encapsulant comprise a first side surface and a second side surface facing each other and a third side surface and a fourth side surface connecting the first side surface and the second side surface and facing each other, the first semiconductor chip and the second semiconductor chip are spaced apart from each other in a direction from the first side surface of the encapsulant to the second side surface of the encapsulant, and the first heat dissipation wire is exposed to the first side surface of the encapsulant and the second heat dissipation wire is exposed to the second side surface of the encapsulant.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, further comprising:
a third heat dissipation wire connected to the first semiconductor chip and exposed to the third side surface of the encapsulant;
a fourth heat dissipation wire connected to the second semiconductor chip and exposed to the third side surface of the encapsulant;
a fifth heat dissipation wire connected to the first semiconductor chip and exposed to the fourth side surface of the encapsulant; and
a sixth heat dissipation wire connected to the second semiconductor chip and exposed to the fourth side surface of the encapsulant.

### Claim 20 (depends on 17)

The semiconductor package of claim 17, wherein the side surfaces of the encapsulant comprise a first side surface and a second side surface facing each other and a third side surface and a fourth side surface connecting the first side surface and the second side surface and facing each other, the first semiconductor chip and the second semiconductor chip are spaced apart from each other in a direction from the first side surface of the encapsulant to the second side surface of the encapsulant, the first heat dissipation wire and the second heat dissipation wire are exposed to the third side surface of the encapsulant, and the semiconductor package further comprises a third heat dissipation wire connected to the first semiconductor chip and penetrating the fourth side surface of the encapsulant and a fourth heat dissipation wire connected to the second semiconductor chip and penetrating the fourth side surface of the encapsulant.