Three-dimensional integrated circuit with top chip including local interconnect for body-source coupling

A structure comprising:

• a chip including:
• first dielectric material layers;
• a first insulator layer;
• a first transistor including a first active device region stacked vertically between the first dielectric material layers and the first insulator layer,
• wherein, within the first active device region, the first transistor includes:
• first drain regions;
• a first source region;
• first channel regions;
• and first body regions on the first channel regions, respectively,
• wherein each first channel region and corresponding first body region on the first channel region are positioned laterally between the first source region and one of the first drain regions, and
• wherein the first transistor further includes first gate structures within the first dielectric material layers immediately adjacent to a surface of the first active device region at the first channel regions, respectively;
• and
• a local interconnect within the first insulator layer immediately adjacent to another surface of the first active device region opposite the first gate structures, wherein the local interconnect electrically couples the first source region and the first body regions.

A method comprising:

• forming a chip including:
• forming a first insulator layer;
• forming a first transistor on the first insulator layer, wherein the first transistor includes:
• a first active device region;
• within the first active device region, a first source region, a first drain region, a first body region adjacent to the first insulator layer, and a first channel region adjacent to the first body region opposite the first insulator, wherein the first body region and the first channel region are positioned laterally between the first source region and the first drain region;
• and
• a first gate structure immediately adjacent to a surface of the first active device region at the first channel region;
• forming first dielectric material layers on the first transistor over the first gate structure;
• forming a trench that extends through the first insulator layer to another surface of the first active device region opposite the first gate structure, wherein the trench exposes the first source region and the first body region;
• and
• forming a local interconnect within the trench immediately adjacent to the first source region and the first body region, wherein the local interconnect electrically couples the first body region and the first source region.