# US 2026/0107752 A1 · Semiconductor package and method of manufacturing the semiconductor package

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- Number: US 2026/0107752 A1
- Document ID: US20260107752A1
- Status: Published application
- Kind: A1
- Application number: 19/243,891
- Filed: 2025-06-20
- Published: 2026-04-16
- Earliest claimed: 2024-10-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sunjae KIM
- Web page: https://patentgrep.com/patent/US20260107752A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 90/20: Configurations of stacked chips
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/7295: {on the rear surface of insulating package substrates, interposers or RDLs, for connection outside of the package, e.g. ball grid array [BGA] bumps}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package may include a lower semiconductor chip; an upper semiconductor chip on the lower semiconductor chip, the upper semiconductor chip including a substrate having a first surface facing the lower semiconductor chip and a second surface opposing the first surface, and a measurement via pattern portion in a peripheral region of the substrate; and a sealing member covering the upper semiconductor chip on the lower semiconductor chip and exposing the second surface of the substrate. The measurement via pattern portion may include first dummy via structures extending from the first surface of the substrate to the second surface such that end portions thereof are exposed from the second surface of the substrate; and second dummy via structures extending from the first surface of the substrate to a depth such that end portions thereof are not exposed from the second surface of the substrate.

## Claims

### Claim 1

A semiconductor package, comprising:
a lower semiconductor chip;
an upper semiconductor chip on the lower semiconductor chip, the upper semiconductor chip including a substrate having a first surface facing the lower semiconductor chip and a second surface opposing the first surface, a front insulating layer on the first surface of the substrate, and a measurement via pattern portion in a peripheral region of the substrate; and
a sealing member covering the upper semiconductor chip on the lower semiconductor chip and exposing the second surface of the substrate, wherein the measurement via pattern portion includes first dummy via structures and second dummy via structures,
the first dummy via structures extend in a thickness direction from the first surface of the substrate to the second surface such that end portions of the first dummy via structures are exposed from the second surface of the substrate, and
the second dummy via structures extend in the thickness direction from the first surface of the substrate to a depth in the substrate such that end portions of the second dummy via structures are not exposed from the second surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein a first group of dummy via structures among the first dummy via structures and the second dummy via structures are respectively arranged at corner portions of the substrate.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein a second group of dummy via structures among the first dummy via structures and the second dummy via structures are respectively arranged at side portions of the substrate.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein a length difference between the first dummy via structures and the second dummy via structures is within a range of 5 μm to 50 μm.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein diameters of the first dummy via structures and the second dummy via structures are within a range of 50 μm to 200 μm.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein
the peripheral region of the substrate has a first width from an outer side surface of the substrate, and
the first width is within a range of 200 μm to 500 μm.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, further comprising:
conductive bumps between the lower semiconductor chip and the upper semiconductor chip, the conductive bumps electrically connecting the lower semiconductor chip to the upper semiconductor chip; and
an adhesive layer filling a space between the conductive bumps and between the lower semiconductor chip and the upper semiconductor chip to attach the lower semiconductor chip and the upper semiconductor chip to each other.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the adhesive layer includes a non-conductive film (NCF).

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the second surface of the substrate and an upper surface of the sealing member are coplanar.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, further comprising:
a package substrate,
wherein the lower semiconductor chip is mounted on the package substrate via conductive bumps.

### Claim 11

A semiconductor package, comprising:
an interposer;
a semiconductor chip on the interposer, the semiconductor chip including a substrate having a first surface facing the interposer and a second surface opposing the first surface, a front insulating layer on the first surface of the substrate, and a measurement via pattern portion in a peripheral region of the substrate; and
a sealing member covering the semiconductor chip, wherein
the sealing member is on the interposer and exposes the second surface of the substrate,
wherein the measurement via pattern portion includes corner measurement pattern portions respectively provided at four corner portions of the substrate,
wherein each of the corner measurement pattern portions includes first dummy via structures and a second dummy via structures,
wherein the first dummy via structures extend in a thickness direction from the first surface of the substrate to the second surface such that end portions of the first dummy via structures are exposed from the second surface of the substrate, and
wherein the second dummy via structures extend in the thickness direction from the first surface of the substrate to a depth in the substrate such that end portions of the second dummy via structures are not exposed from the second surface of the substrate.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein a length difference between the first dummy via structures and the second dummy via structures is within a range of 5 μm to 50 μm.

### Claim 13 (depends on 11)

The semiconductor package of claim 11, wherein diameters of the first dummy via structures and second dummy via structures are within a range of 50 μm to 200 μm.

### Claim 14 (depends on 11)

The semiconductor package of claim 11, wherein
the peripheral region of the substrate has a first width from an outer side surface of the substrate, and
the first width is within a range of 200 μm to 500 μm.

### Claim 15 (depends on 11)

The semiconductor package in claim 11, further comprising:
side measurement pattern portions respectively provided at four side portions of the substrate, wherein
each of the side measurement pattern portions includes third dummy via structure and fourth dummy via structures,
the third dummy via structures extend in the thickness direction from the first surface of the substrate to the second surface of the substrate such that end portions of the third dummy via structures are exposed from the second surface of the substrate, and
the fourth dummy via structures extend in the thickness direction from the first surface of the substrate to a distance, the distance being less than a thickness of the substrate, such that end portions of the fourth dummy via structures are not exposed from the second surface of the substrate.

### Claim 16 (depends on 11)

The semiconductor package of claim 11, further comprising:
conductive bumps between the interposer and the semiconductor chip, the conductive bumps electrically connecting the interposer to the semiconductor chip; and
an underfill member filling a space between the conductive bumps, wherein
the underfill member is between the interposer and the semiconductor chip.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein the underfill member includes an epoxy material.

### Claim 18 (depends on 11)

The semiconductor package of claim 11, wherein the second surface of the substrate and an upper surface of the sealing member are coplanar.

### Claim 19 (depends on 11)

The semiconductor package of claim 11, further comprising:
a package substrate,
wherein the interposer is mounted on the package substrate via conductive bumps.

### Claim 20

A semiconductor package, comprising:
a first semiconductor chip;
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip having a central region and a peripheral region surrounding the central region, the second semiconductor chip including a measurement via pattern portion in the peripheral region; and
a sealing member covering the second semiconductor chip, the sealing member being on the first semiconductor chip and exposing an upper surface of the second semiconductor chip,
wherein the measurement via pattern portion includes corner measurement pattern portions respectively provided at four corner portions of the second semiconductor chip and side measurement pattern portions respectively provided at four side portions of the second semiconductor chip, and
wherein each of the corner measurement pattern portions and the side measurement pattern portions includes first dummy via structures and second dummy via structures,
wherein the first dummy via structures extend into at least a portion of the second semiconductor chip in a thickness direction such that end portions of the first dummy via structures are exposed from the upper surface of the second semiconductor chip, and
wherein the second dummy via structures extend partially through the second semiconductor chip in the thickness direction such that end portions of the second dummy via structures are not exposed from the upper surface of the second semiconductor chip.