# US 2026/0107751 A1 · Semiconductor device with polymer liner and method for fabricating the same

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- Number: US 2026/0107751 A1
- Document ID: US20260107751A1
- Status: Published application
- Kind: A1
- Application number: 18/948,809
- Filed: 2024-11-15
- Published: 2026-04-16
- Earliest claimed: 2024-10-16
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: KUO-HUI SU
- Web page: https://patentgrep.com/patent/US20260107751A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 90/00: Package configurations
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate comprising a front side and a back side parallel to the front side; a bonding dielectric positioned on the front side of the first substrate; a redistribution layer positioned between the bonding dielectric and the front side of the first substrate; a first dielectric layer positioned between the front side of the first substrate and the redistribution layer; a capping layer positioned between the redistribution layer and the bonding layer; a first conductive pad positioned between the capping layer and the bonding layer; a second dielectric layer positioned between the capping layer and the bonding layer, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature positioned in the bonding dielectric and the first conductive pad.

## Claims

### Claim 1

A semiconductor device, comprising:
a first semiconductor chip comprising a first substrate having a front side and a back side parallel to the front side;
a bonding dielectric positioned over the front side of the first substrate and a second passivation layer positioned over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate;
a redistribution layer positioned between the bonding dielectric and the front side of the first substrate;
a first dielectric layer positioned between the front side of the first substrate and the redistribution layer;
a capping layer positioned between the redistribution layer and the bonding layer;
a first conductive pad positioned between the capping layer and the bonding layer;
a second dielectric layer positioned between the capping layer and the bonding layer, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad;
a conductive feature positioned in the bonding dielectric and the first conductive pad;
a through substrate via (TSV) exposed through the second passivation layer and electrically coupled to the conductive feature;
a polymer liner positioned between the TSV and the first substrate;
a barrier layer positioned between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the conductive feature and the TSV;
an adhesion layer positioned between the barrier layer and the TSV; and
a second semiconductor chip coupled to the first semiconductor chip at a bonding interface and comprising a second substrate coupled to the first substrate;
wherein the polymer liner of the first semiconductor chip is separate from the bonding interface;
wherein the first semiconductor chip further comprises an isolation liner positioned between the barrier layer and the second passivation layer and between the polymer liner and the first substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the conductive feature includes a second conductive pad exposed through a back side of the bonding dielectric and an interconnect structure electrically connected to the second conductive pad and penetrating through the first conductive pad.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a top connector positioned over the conductive feature.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a top barrier layer positioned between the top connector and the conductive feature.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising a top passivation layer positioned over the back side of the bonding dielectric, wherein the top barrier layer is positioned in the top passivation layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the top passivation layer comprises polybenzoxazole, polyimide, benzocyclobutene, solder resist film, or a combination thereof.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the top barrier layer comprises aluminum fluoride and zinc oxide.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein a concentration of zinc oxide in the top barrier layer is greater than a concentration of aluminum fluoride in the top barrier layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the redistribution layer includes a plurality of horizontal segments parallel to the front side of the first substrate and a plurality of vertical segments parallel to a surface of the isolation liner.

### Claim 10

A method for fabricating a semiconductor device, comprising:
forming a conductive feature and a bonding dielectric over a front side of a first substrate, wherein the conductive feature is formed in the bonding dielectric;
forming a redistribution layer between the bonding dielectric and the front side of the first substrate;
forming a second passivation layer over a back side of the first substrate;
forming a first recess in a top surface of the second passivation layer to expose the conductive feature;
conformally forming an isolation liner on a sidewall of the first recess;
performing a pulsed etching operation to conformally form a polymer liner on a sidewall of the isolation liner, wherein a top surface of the polymer liner is lower than the top surface of the second passivation layer;
conformally forming a barrier layer over the polymer liner and the isolation liner;
conformally forming an adhesion layer over the barrier layer; and
forming a conductive material in the first recess to form a through substrate via (TSV).

### Claim 11 (depends on 10)

The method of claim 10, further comprising thinning the first substrate on a back side of the first substrate before forming the second passivation layer.

### Claim 12 (depends on 10)

The method of claim 10, further comprising coupling a second substrate to the first substrate by performing a hybrid bonding operation after the formation of the through substrate via.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming a top connector over the conductive feature after the coupling of the second substrate to the first substrate.

### Claim 14 (depends on 13)

The method of claim 13, wherein the redistribution layer includes a plurality of horizontal segments parallel to the front side of the first substrate and a plurality of vertical segments parallel to a surface of the isolation liner.

### Claim 15 (depends on 14)

The method of claim 14, wherein the step of forming the conductive feature and the bonding dielectric over the front side of the first substrate further comprises forming a first dielectric layer between the front side of the first substrate and the redistribution layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the step of forming the conductive feature and the bonding dielectric over the front side of the first substrate further comprises forming a capping layer between the redistribution layer and the bonding layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the step of forming the conductive feature and the bonding dielectric over the front side of the first substrate further comprises forming a first conductive pad between the capping layer and the bonding layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the step of forming the conductive feature and the bonding dielectric over the front side of the first substrate further comprises forming a second dielectric layer between the capping layer and the bonding layer, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad.

### Claim 19 (depends on 18)

The method of claim 18, wherein the conductive feature includes a second conductive pad exposed through a back side of the bonding dielectric and an interconnect structure electrically connected to the second conductive pad and penetrating through the first conductive pad.