# US 2026/0107692 A1 · Memory Device With Source Lines in Parallel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0107692 A1 - Document ID: US20260107692A1 - Status: Published application - Kind: A1 - Application number: 19/419,855 - Filed: 2025-12-15 - Published: 2026-04-16 - Earliest claimed: 2019-10-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Ku-Feng Lin - Web page: https://patentgrep.com/patent/US20260107692A1 ## CPC - G11C 11/2253: {Address circuits or decoders} - H10N 50/80: Constructional details - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - G11C 11/1653: {Address circuits or decoders} - G11C 11/1655: {Bit-line or column circuits} - G11C 11/1657: {Word-line or row circuits} - G11C 11/1659: {Cell access} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/2259: {Cell access} - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 13/0023: {Address circuits or decoders} - G11C 13/003: {Cell access} - G11C 13/004: {Reading or sensing circuits or methods} - H10B 61/22: {of the field-effect transistor [FET] type} - H10N 50/01: Manufacture or treatment - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 8/14: Word line organisation; Word line lay-out - G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials - G11C: STATIC STORES (semiconductor memory devices H10B) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel. ## Claims ### Claim 1 A method for performing a write operation or read operation in a memory cell, comprising: selectively providing a word line signal to a selection device from a selected word line of a plurality of word lines; selectively providing a bit line signal to a storage device connected in series to the selection device from a selected bit line of a plurality of bit lines; selectively providing a source line signal to the selection device from a selected source line of a plurality of source lines, wherein a first number of source lines of the plurality of source lines are connected in parallel; and switching the storage device from a first resistance state to a second resistance state. ### Claim 2 (depends on 1) The method of claim 1, wherein the first number of source lines are connected in parallel through one or more metal contact tracks that extend perpendicular to the first number of source lines. ### Claim 3 (depends on 2) The method of claim 2, further comprising: providing a plurality of third metal tracks above and intersecting with the first number of source lines of the plurality of source lines; and connecting the first number of source lines of the plurality of source lines in parallel through the plurality of third metal tracks. ### Claim 4 (depends on 1) The method of claim 1, wherein the first number of source lines are determined based on a first sheet resistance associated with the plurality of bit lines and a second sheet resistance associated with the plurality of source lines. ### Claim 5 (depends on 4) The method of claim 4, wherein the storage device is a magnetic tunnel junction (MTJ), and the selection device includes two transistors. ### Claim 6 (depends on 1) The method of claim 1, wherein the first resistance state is indicative of a low data value, and the second resistance state is indicative of a high data value. ### Claim 7 (depends on 1) The method of claim 1, wherein switching from the first resistance state to the second resistance state causes a bit of data to be written and stored in the memory cell. ### Claim 8 (depends on 7) The method of claim 7, further comprising switching from the second resistance state to the first resistance state, wherein switching from the second resistance state to the first resistance state causes the bit of data to be read from the memory cell. ### Claim 9 (depends on 1) The method of claim 1, wherein a first number of the plurality of source lines are connected in parallel, and wherein the first number is determined based on a first sheet resistance associated with the plurality of bit lines and a second sheet resistance associated with the plurality of source lines. ### Claim 10 A memory device, comprising: a word-line driver configured to selectively provide a word line signal from a selected word line of a plurality of word lines; bit-line driver configured to provide a bit line signal from a selected bit line of a plurality of bit lines; a source-line driver configured to selectively provide a source line signal on a selected source line of a plurality of source lines, wherein a first number of source lines of the plurality of source lines are connected in parallel, the first number being determined based on a first sheet resistance associated with the plurality of bit lines and a second sheet resistance associated with the plurality of source lines; and a memory cell including: a storage device coupled to the bit-line driver, the storage device being selectable between a first resistance state and a second resistance state in response to the bit line signal at the selected bit line; and a selection device connected in series with the storage device and coupled to the source-line driver and the word-line driver, the selection device coupling the storage device to the selected source line based on receiving the word line signal. ### Claim 11 (depends on 10) The memory device of claim 10, wherein the first number of source lines are connected in parallel through one or more metal contact tracks that extend perpendicular to the first number of source lines. ### Claim 12 (depends on 11) The memory device of claim 11, further comprising: a plurality of third metal tracks above and intersecting with the first number of source lines of the plurality of source lines; wherein the first number of source lines of the plurality of source lines are connected in parallel through the plurality of third metal tracks. ### Claim 13 (depends on 10) The memory device of claim 10, wherein the storage device is a magnetic tunnel junction (MTJ), and the selection device includes two transistors. ### Claim 14 (depends on 10) The memory device of claim 10, wherein the first resistance state is indicative of a low data value, and the second resistance state is indicative of a high data value. ### Claim 15 (depends on 10) The memory device of claim 10, wherein switching from the first resistance state to the second resistance state causes a bit of data to be written and stored in the memory cell. ### Claim 16 (depends on 15) The memory device of claim 15, wherein switching from the second resistance state to the first resistance state causes the bit of data to be read from the memory cell. ### Claim 17 A method, comprising: obtaining a first sheet resistance of a bit line metal track; obtaining a second sheet resistance of a source line metal track; determining a first number of source lines of a plurality of source lines based on the first sheet resistance and the second sheet resistance; connecting the first number of source lines in parallel; and selectively providing a source line signal from a selected source line of the plurality of source lines to a selection device. ### Claim 18 (depends on 17) The method of claim 17, wherein the first number of source lines are connected in parallel through one or more metal contact tracks that extend perpendicular to the first number of source lines. ### Claim 19 (depends on 18) The method of claim 18, further comprising: providing a plurality of third metal tracks above and intersecting with the first number of source lines of the plurality of source lines; and connecting the first number of source lines of the plurality of source lines in parallel through the plurality of third metal tracks. ### Claim 20 (depends on 17) The method of claim 17, further comprising: providing a word line signal to the selection device to couple a storage device to the selected source line.