Pixel and image sensor including the same

An image sensor comprising:

• a pixel array including a plurality of pixels configured to perform a sensing operation by collecting photo-charges generated by incident light;
• a row driver configured to drive the pixel array in units of rows;
• and
• a controller configured to control the pixel array and the row driver,
• wherein a pixel of the plurality of pixels comprises
• a first photoelectric conversion region and a second photoelectric conversion region in a lower portion of a semiconductor substrate, the first photoelectric conversion region and the second photoelectric conversion region spaced apart from each other in a first horizontal direction,
• a first floating diffusion region and a second floating diffusion region in an upper portion of the semiconductor substrate,
• a first transfer gate and a second transfer gate above the semiconductor substrate,
• a first pixel transistor on a side of the first transfer gate in a second horizontal direction perpendicular to the first horizontal direction, the first pixel transistor including a first source-drain region in the upper portion of the semiconductor substrate, a second source-drain region in the upper portion of the semiconductor substrate, and a first pixel gate above the semiconductor substrate and between the first source-drain region and the second source-drain region, and the second source-drain region is configured to receive a pixel power voltage, and
• a bridge region below the second source-drain region, the bridge region configured to form an overflow barrier potential such that redundant photo-charges from the first photoelectric conversion region and the second photoelectric conversion region are discharged to the second source-drain region.

A pixel of an image sensor, comprising:

• a first photoelectric conversion region in a lower portion of a semiconductor substrate;
• a first floating diffusion region in an upper portion of the semiconductor substrate;
• a first transfer gate above the semiconductor substrate;
• a second photoelectric conversion region in the lower portion of the semiconductor substrate, the second photoelectric conversion region spaced apart from the first photoelectric conversion region in a first horizontal direction;
• a second floating diffusion region in the upper portion of the semiconductor substrate, the second floating diffusion region spaced apart from the first floating diffusion region in the first horizontal direction:
• a second transfer gate above the semiconductor substrate, the second transfer gate spaced apart from the first transfer gate in the first horizontal direction;
• a first source-drain region and a second source-drain region in the upper portion of the semiconductor substrate, the second source-drain region configured to receive a pixel power voltage;
• a first pixel gate above the semiconductor substrate and between the first source-drain region and the second source-drain region;
• a third source-drain region and a fourth source-drain region in the upper portion of the semiconductor substrate, the fourth source-drain region configured to receive the pixel power voltage;
• a second pixel gate above the semiconductor substrate and between the third source-drain region and the fourth source-drain region;
• and
• at least one bridge region below at least one of the second source-drain region or the fourth source-drain region, the at least one bridge region configured to form an overflow barrier potential such that redundant photo-charges from the first photoelectric conversion region and the second photoelectric conversion region are discharged to the at least one of the second source-drain region or the fourth source-drain region.