Semiconductor structure and method for forming the same

A semiconductor structure, comprising:

• a substrate;
• and
• a first complementary metal-oxide-semiconductor (CMOS) device, comprising a first transistor and a second transistor formed on the substrate,
• wherein the first transistor comprises:
• first nanostructures, vertically arranged over the substrate;
• a first gate structure, wrapped around each of the first nanostructures;
• first source/drain features, attached to opposite sides of the first nanostructures, wherein each of the first source/drain features comprises a first bottom dielectric layer and a first epitaxial layer over the first bottom dielectric layer;
• and
• a second bottom dielectric layer, formed over the substrate and below the first gate structure, wherein the second bottom dielectric layer is vertically sandwiched between the substrate and the first gate structure;
• wherein the second transistor comprises:
• second nanostructures, vertically arranged over the substrate;
• a second gate structure, wrapped around each of the second nanostructures and engaging with the first gate structure;
• second source/drain features, attached to opposite sides of the second nanostructures, wherein each of the second source/drain features comprises a second epitaxial layer;
• and
• a third bottom dielectric layer, formed over the substrate and below the second gate structure, wherein the third bottom dielectric layer is vertically sandwiched between the substrate and the second gate structure.

A method of forming a semiconductor structure, comprising:

• forming a fin structure over a substrate, wherein the fin structure comprises a first semiconductor layer over the substrate, and second semiconductor layers and third semiconductor layers stacked in an alternating manner over the first semiconductor layer;
• forming a dummy gate structure over the fin structure;
• forming source/drain trenches in the fin structure on opposite sides of the dummy gate structure;
• removing the first semiconductor layer through the source/drain trenches to form a first recess;
• depositing a first dielectric material in the first recess to form a first bottom dielectric layer;
• forming a second bottom dielectric layer in each of the source/drain trenches;
• forming a first epitaxial layer on the second bottom dielectric layer in each of the source/drain trenches, such that the second bottom dielectric layer is vertically between the substrate and the first epitaxial layer;
• removing the dummy gate structure and the second semiconductor layers to form a gate trench, wherein the gate trench exposes a first portion of a top surface of the first bottom dielectric layer;
• and
• forming a gate structure in the gate trench, wherein the gate structure is wrapped around each of the third semiconductor layers, and covers the first portion of the top surface of the first bottom dielectric layer.