High voltage finfet device and method

A method, comprising:

• forming a deep P-well in a substrate;
• forming a fin over the deep P-well and the substrate;
• and
• forming a transistor device in the fin, the transistor device comprising:
• a source region and a drain region,
• a first gate structure disposed on a first channel region in the substrate and comprising a first gate dielectric disposed on the first channel region and a first gate electrode disposed on the first gate dielectric,
• a second gate structure disposed on a second channel region in the substrate and between the first gate structure and the drain region;
• an interlayer dielectric layer region between the first gate structure and the second gate structure;
• and
• a metal layer over the interlayer dielectric layer region;
• wherein the second channel region comprises an N-well and wherein the second channel region is disposed on the deep P-well.

A semiconductor device, comprising:

• a source region and a drain region in a substrate;
• a first gate structure disposed on the substrate and between the source region and the drain region closer to the source region;
• and
• a second gate structure disposed on the substrate and between the source region and the drain region closer to the drain region, the second gate structure having a first oxide layer, a trapping layer comprising small band gap material over the first oxide layer, and a second oxide layer over the trapping layer.