Self-test mechanisms for end-of-life detection and response for circuit interrupter devices
AssigneeZe CHEN
InventorsZe CHEN, Gui CHEN
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Abstract
A circuit for a circuit interrupter is provided. The circuit may in include a first SCR configured to receive a first trigger signal at a gate of the first SCR, a second SCR configured to receive a second trigger signal at a gate of the second SCR, and a third SCR configured to receive a third trigger signal at a gate of the third SCR. A cathode of the first SCR may be connected to an anode of the third SCR. A cathode of the second SCR and a cathode of the third SCR may be connected to a ground. Methods of operating a circuit interrupter and a circuit are also provided.
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A circuit for a circuit interrupter, comprising:
- a plurality of SCRs, including a first SCR, a second SCR, and a third SCR;
- a circuit board with first mounting area for a mounted SCR of the plurality of SCRs, the mounting area having first, second, third, and fourth conductive traces;
- and
- a microcontroller,
- wherein:
- the first SCR is configured to receive a first trigger signal at a gate of the first SCR;
- the second SCR configured to receive a second trigger signal at a gate of the second SCR;
- the third SCR configured to receive a third trigger signal at a gate of the third SCR;
- a cathode of the first SCR is connected to an anode of the third SCR;
- a cathode of the second SCR and a cathode of the third SCR are connected to a ground;
- an anode of the first SCR and an anode of the second SCR are configured to receive power from a neutral line;
- the mounted SCR is mounted on the first mounting area;
- a gate of the mounted SCR is connected to the first conductive trace;
- a cathode of the mounted SCR is connected to the third conductive trace;
- an anode of the mounted SCR is connected to both the second conductive trace and the fourth conductive trace;
- and
- the microcontroller is configured to generate the first, second, and third trigger signals.
A circuit for a circuit interrupter, comprising:
- a plurality of SCRs, including a first SCR, a second SCR, and a third SCR;
- a first transistor;
- a circuit board with first mounting area for the first transistor, the mounting area having first, second, third, and fourth conductive traces;
- and
- a microcontroller,
- wherein:
- the first SCR is configured to receive a first trigger signal at a gate of the first SCR;
- the second SCR configured to receive a second trigger signal at a gate of the second SCR;
- the third SCR configured to receive a third trigger signal at a gate of the third SCR;
- a cathode of the first SCR is connected to an anode of the third SCR;
- a cathode of the second SCR and a cathode of the third SCR are connected to a ground;
- an anode of the first SCR and an anode of the second SCR are configured to receive power from a neutral line;
- the first transistor is mounted on the first mounting area;
- a collector gate of the first transistor is connected to the first conductive trace;
- an emitter of the first transistor is connected to the third conductive trace;
- a base of the first transistor is connected to both the second conductive trace and the fourth conductive trace;
- and
- the microcontroller is configured to generate the first, second, and third trigger signals.
Dependencies are inferred from the claim text.