Nonvolatile memory device and storage device

A nonvolatile memory device comprising:

• a memory cell array including a plurality of memory planes that include a first memory plane and a second memory plane;
• a plurality of page buffer circuits corresponding to the plurality of memory planes, each of the plurality of page buffer circuits connected to a respective one of the plurality of memory planes through corresponding bit-lines;
• a data input/output (I/O) circuit connected to the plurality of page buffer circuits through corresponding data lines;
• a chip enable interface circuit;
• a chip interface pin connected to the chip enable interface circuit;
• and
• a control circuit configured to control an operation of the nonvolatile memory device,
• wherein the control circuit is configured to, based on a first data output command from a storage controller,
• perform a first direct memory access (DMA) operation to output a first read data from the first memory plane to a storage controller through the data I/O circuit, and
• receive a second data output command from the storage controller based on the first DMA operation is being performed,
• wherein the chip enable interface circuit is configured to generate a self termination signal indicating that the first DMA operation is completed based on a first start address associated with the first read data and generate a self enable signal based on the self termination signal, and
• wherein the control circuit is configured to, in response to the second data output command and the self enable signal, perform a second DMA operation to output a second read data from the second memory plane to the storage controller through the data I/O circuit.

A storage device comprising:

• a plurality of nonvolatile memory chips including at least a first nonvolatile memory chip and a second nonvolatile memory chip,
• a storage controller configured to control the plurality of nonvolatile memory chips,
• wherein the first nonvolatile memory chip includes a first memory cell array, a first chip enable interface circuit, a first chip interface pin connected to the first chip enable interface circuit and a first control circuit configured to control an operation of the first nonvolatile memory chip,
• wherein the first nonvolatile memory chip is configured to, based on a first data output command from the storage controller, perform a first direct memory access (DMA) operation to transmit a first read data from the first memory cell array to the storage controller,
• wherein the first chip enable interface circuit is configured to generate a first self termination signal indicating that the first DMA operation is completed based on a first start address associated with the first read data, and provide the first self termination signal to the second nonvolatile memory chip through the first chip interface pin,
• wherein the second nonvolatile memory chip includes a second memory cell array and a second chip interface pin configured to receive the first self termination signal, and
• wherein the second nonvolatile memory chip is configured to:
• be self-enabled based on the first self termination signal from the first nonvolatile memory chip;
• and
• perform a second DMA operation to transmit a second read data from the second memory cell array to the storage controller based on a second data output command, wherein the second nonvolatile memory chip is configured to receive the second data output command from the storage controller during the first nonvolatile memory chip performing the first DMA operation.