Back to results
US 2026/0104984 A1Published application
Software breakpoint for shared code regions in a multi-processor architecture
AssigneeQUALCOMM Incorporated
InventorsAmey MAHAJAN, Jeremy GILBERT, Richard SENIOR, Jing LIU
Life of this patent
Estimating the term…
Abstract
Aspects of the disclosure are directed to software breakpoint insertion in shared code regions. In accordance with one aspect, the disclosure includes setting a new instruction to a trap instruction in a local cache memory using a software breakpoint; locking a cache line in the local cache memory to generate a locked cache line; writing the trap instruction to a memory location specified by the locked cache line; and fetching the trap instruction from the local cache memory to start a diagnostic process.
Claims20
A method comprising:
- setting a new instruction to a trap instruction in a local cache memory using a software breakpoint;
- locking a cache line in the local cache memory to generate a locked cache line;
- writing the trap instruction to a memory location specified by the locked cache line;
- and
- fetching the trap instruction from the local cache memory to start a diagnostic process.
2 more elements
An apparatus comprising:
- a cache memory configured to store an original instruction, wherein the original instruction is specified by a virtual address;
- and
- a core processing engine coupled to the cache memory, the core processing engine configured to lock a cache line in the cache memory to generate a locked cache line.
An apparatus comprising:
- means for setting a new instruction to a trap instruction in a local cache memory using a software breakpoint;
- means for locking a cache line in the local cache memory to generate a locked cache line;
- means for writing the trap instruction to a memory location specified by the locked cache line;
- and
- means for fetching the trap instruction from the local cache memory to start a diagnostic process.
2 more elements
Dependencies are inferred from the claim text.