Ai inference compiler and runtime tool chain

A method comprising:

• transmitting, by a processor of a system-on-chip (SOC), an initial timing message to a first microcontroller at an initial time according to a kernel clock of the processor;
• receiving, by the processor, a response message from the first microcontroller indicating a response time at a first controller clock of the first microcontroller;
• in response to receiving the response message, determining, by the processor, a completion time according to the kernel clock of the processor;
• computing, by the processor, an error rate for the kernel clock representing a difference between the kernel clock of the processor and the first controller clock of the first microcontroller, based upon the initial clock time, the completion time, and the response time;
• and
• adjusting, by the processor, a frequency of the kernel clock based upon the error rate to reduce the error rate between the kernel clock and the first controller clock.

An ego comprising:

• a circuit board comprising a plurality of system-on-chip (SOC) devices and a plurality of microcontrollers corresponding to the SOC devices;
• a first microcontroller configured to:
• transmit an initial timing message to a second microcontroller at an initial time according to a first controller clock of the first microcontroller;
• receive a response message from the second microcontroller indicating a response time at a second controller clock of the second microcontroller;
• determine a completion time according to the first controller clock of the first microcontroller, in response to receiving the response message from the second microcontroller;
• compute an error rate representing a difference between the first controller clock of the first microcontroller and the second controller clock of the second microcontroller, based upon the initial clock time, the completion time, and the response time;
• and
• adjust a frequency of the second controller clock based upon the error rate to reduce the error rate between the first controller clock and the second controller clock.

A method comprising:

• transmitting, by a first microcontroller coupled to a first SOC, an initial timing message to a second microcontroller coupled to a second SOC at an initial time according to a first controller clock of the first microcontroller;
• receiving, by the first microcontroller, a response message from the second microcontroller indicating a response time at a second controller clock of the second microcontroller;
• determining, by the first microcontroller, a completion time according to the first controller clock of the first microcontroller, in response to receiving the response message from the second microcontroller;
• computing, by the first microcontroller, an error rate representing a difference between the first controller clock of the first microcontroller and the second controller clock of the second microcontroller, based upon the initial clock time, the completion time, and the response time;
• and
• adjusting, by the first microcontroller, a frequency of the second controller clock based upon the error rate to reduce the error rate between the first controller clock and the second controller clock.