US 2026/0104859 A1 · PROCESSING UNIT, PROCESSING-IN-MEMORY DEVICE, AND PROCESSING-IN-MEMORY SYSTEM BASED ON REDUNDANT RESIDUE NUMBER SYSTEM

Abstract

A processing unit includes a redundant residue number generation circuit configured to convert first operand data and second operand data into a plurality of first operand redundant residue number sets, and a plurality of second operand redundant residue number sets based on a redundant residue number system (RRNS) using first to T-th moduli. T is a natural number equal to or greater than four. The processing unit includes a plurality of arithmetic circuits configured to perform operations using the plurality of first operand redundant residue number sets and the plurality of second operand redundant residue number sets, and a reconstruction circuit configured to recover result data based on the RRNS into result data based on a weighted number system.

Claims76

Dependent claims

A processing unit comprising:

a redundant residue number generation circuit configured to convert first operand data and second operand data into a plurality of first operand redundant residue number sets and a plurality of second operand redundant residue number sets based on a redundant residue number system (RRNS) using first to T-th moduli, wherein T is a natural number equal to or greater than four;
a plurality of arithmetic circuits configured to perform operations using the plurality of first operand redundant residue number sets and the plurality of second operand redundant residue number sets;
and
a reconstruction circuit configured to recover result data based on the RRNS into result data based on a weighted number system.

1 more element

A processing-in-memory (PIM) device comprising:

a redundant residue number generation circuit configured to receive data in an 8-bit integer format from a host, perform modular operations on unsigned data excluding a sign bit using first to T-th moduli to generate first to T-th redundant residues based on a redundant residue number system (RRNS), and to output the redundant residues together with the sign bit;
a memory circuit configured to receive and store the sign bit and the first to T-th redundant residues output from the redundant residue number generation circuit;
and
a processing unit configured to receive the sign bit and the first to T-th redundant residues from the memory circuit as operands and to perform multiplication and accumulation (MAC) operations,
wherein T is a natural number equal to or greater than four.

2 more elements

A processing-in-memory (PIM) system comprising:

a host including a redundant residue number generation circuit configured to perform modular operations on unsigned write data, that excludes a sign bit of write data in an 8-bit signed integer format, using first to T-th moduli, wherein T is a natural number equal to or greater than four, to generate first to T-th redundant residues based on a redundant residue number system (RRNS), and to output the redundant residues together with the sign bit;
and
a PIM device including a memory circuit configured to receive and store the sign bit and the first to T-th redundant residues output from the host, and a processing unit configured to receive the sign bit and the first to T-th redundant residues from the memory circuit as operands and to perform multiplication and accumulation (MAC) operations.

Dependencies are inferred from the claim text.

Processing unit, processing-in-memory device, and processing-in-memory system based on redundant residue number system

Life of this patent

Processing unit, processing-in-memory device, and processing-in-memory system based on redundant residue number system

Life of this patent

Abstract

Claims76