Memory system for processing artificial neural network and control method thereof
AssigneeDeepx Co., Ltd.
InventorLok Won KIM
Life of this patent
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Abstract
According to an example of the present disclosure, a system is provided. A system may include a processor configured to output a memory control signal including an artificial neural network data locality, and a memory controller configured to receive the memory control signal from the processor and control a main memory in which data of an artificial neural network model corresponding to the artificial neural network data locality, is stored.
Claims20
A memory system comprising:
- a processor circuit configured to generate a memory access request, the memory access request including identification information distinct from a physical address;
- and
- a memory controller circuit electrically coupled to the processor circuit and configured to control at least one main memory comprising a plurality of banks;
- wherein the memory controller circuit is configured to determine a target bank subset from the plurality of banks based on the identification information, and map the memory access request to the target bank subset.
A memory controller for processing an artificial neural network (ANN), comprising:
- an interface configured to receive a memory access request including identification information distinct from a physical address from a processor;
- and
- a control circuit configured to determine an active bank subset among a plurality of banks of at least one main memory based on the identification information;
- wherein the control circuit is configured to:
- identify remaining banks of the plurality of banks that are not included in the active bank subset as idle banks;
- and transmit a command or control signal to the at least one main memory to restrict a refresh operation for the idle banks.
A method of controlling at least one main memory comprising a plurality of banks, the method comprising:
- receiving a memory access request and identification information associated with the memory access request from a processor, wherein the identification information is distinct from a physical address;
- analyzing the identification information to determine a data attribute including at least one of a domain type, an artificial neural network (ANN) model identifier, a thread identifier, quantization information, or an operation type indicating a learning phase or an inference phase;
- dynamically determining a target bank subset from the plurality of banks to be allocated to the memory access request based on the determined data attribute;
- and
- mapping the memory access request to the target bank subset;
- wherein the determining includes allocating different bank subsets to different domain types or different ANN model identifiers to isolate memory accesses or maximize bank interleaving efficiency.
Dependencies are inferred from the claim text.