US 2026/0104455 A1Published application

Clock control circuit and method

AssigneeRealtek Semiconductor Corp.

InventorsYu-Ting LI, Pei-Ying HSUEH, Ying-Yen CHEN

Life of this patent

Estimating the term…

Loading patent…

Abstract

A clock control circuit for a circuitry, including a scan flip-flop circuit, an at-speed domain and a timing exception domain, includes a first gate control circuit, a first gate circuit, a second gate control circuit and a second gate circuit. The first gate circuit is controlled by a first control signal output by the first gate control circuit, a scan enable signal and a scan mode signal to block or output a clock signal to the scan flip-flop circuit. The second gate circuit is controlled by a second control signal output by the second gate control circuit to block or output an output signal of the scan flip-flop circuit to the timing exception domain. When the scan mode signal has a first logic value, the second control signal switches between the first logic value and a second logic value according to a test pattern.

Claims20

Dependent claims

A clock control circuit, configured for controlling a circuitry, the circuitry comprising a scan flip-flop circuit, an at-speed domain and a timing exception domain, the scan flip-flop circuit being configured to output data to the at-speed domain and the timing exception domain, the clock control circuit comprising:

a first gate control circuit, configured to be controlled by a scan mode signal, and configured to output a first control signal;
a first gate circuit, coupled to the first gate control circuit and the scan flip-flop circuit, the first gate circuit being configured to be controlled by the first control signal, a scan enable signal and the scan mode signal, and configured to block or output a clock signal to the scan flip-flop circuit;
a second gate control circuit, coupled to the first gate control circuit, the second gate control circuit being configured to be controlled by the scan mode signal and configured to output a second control signal, wherein when the scan mode signal has a first logic value, the second control signal switches between the first logic value and a second logic value different from the first logic value according to a test pattern for testing the circuitry;
and
a second gate circuit, coupled to the scan flip-flop circuit, the second gate control circuit and the timing exception domain, the second gate circuit being configured to be controlled by the second control signal, and configured to block or output an output signal of the scan flip-flop circuit to the timing exception domain.

2 more elements

A clock control method for a circuitry, wherein the circuitry comprises a scan flip-flop circuit, an at-speed domain and a timing exception domain, the scan flip-flop circuit is configured to output data to the at-speed domain and the timing exception domain, and the clock control method comprises:

by a first gate control circuit, outputting a first control signal according to the control of a scan mode signal;
by a first gate circuit coupled to the first gate control circuit and the scan flip-flop circuit, blocking or outputting a clock signal to the scan flip-flop circuit according to the control of the first control signal, a scan enable signal and the scan mode signal;
by a second gate control circuit coupled to the first gate control circuit, outputting a second control signal according to the control of the scan mode signal, wherein when the circuitry operates in a capture phase of a scan test, the second control signal switches between a first logic value and a second logic value according to a test pattern for testing the circuitry;
and
by a second gate circuit coupled to the scan flip-flop circuit, the second gate control circuit and the timing exception domain, blocking or outputting an output signal of the scan flip-flop circuit to the timing exception domain according to the control of the second control signal.

2 more elements

Dependencies are inferred from the claim text.