# US 2026/0101807 A1 · Semiconductor package

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- Number: US 2026/0101807 A1
- Document ID: US20260101807A1
- Status: Published application
- Kind: A1
- Application number: 19/170,634
- Filed: 2025-04-04
- Published: 2026-04-09
- Earliest claimed: 2024-10-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yubin SONG; Pilkyu KANG; Jaewha PARK; Eunmi KIM; Kunsang PARK
- Web page: https://patentgrep.com/patent/US20260101807A1

## CPC

- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/00: Package configurations
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes: a semiconductor chip including through-electrodes penetrating through a substrate, and back pads on the through-electrodes; a side passivation layer around the semiconductor chip, and extending along the side surface of the substrate; a gap-fill dielectric layer covering at least a portion of the side passivation layer; a bonding dielectric layer on the gap-fill dielectric layer; and a top semiconductor chip on the semiconductor chip, and including a bonding insulating layer contacting the bonding dielectric layer. The through-electrodes have first upper portions protruding to the back surface of the substrate, the side passivation layer has a second upper portion protruding to the back surface of the substrate and spaced apart from the first upper portions in a horizontal direction. The gap-fill dielectric layer fills a space between the first upper portions and the second upper portion.

## Claims

### Claim 1

A semiconductor package comprising:
a semiconductor chip comprising:
a substrate comprising a front surface, a back surface opposite to the front surface, and a side surface extending between the front surface and the back surface;
front pads disposed on the front surface;
through-electrodes electrically connected to the front pads and penetrating through the substrate; and
back pads disposed on the through-electrodes;
a side passivation layer around the semiconductor chip and extending along the side surface of the substrate;
a gap-fill dielectric layer on the back surface of the substrate and covering at least a portion of each of the through-electrodes and the side passivation layer;
a bonding dielectric layer on the gap-fill dielectric layer and contacting at least a portion of each of the back pads; and
a top semiconductor chip on the semiconductor chip, the top semiconductor chip comprising:
connection pads contacting the back pads; and
a bonding insulating layer contacting at least a portion of each of the connection pads and contacting the bonding dielectric layer,
wherein the through-electrodes have first upper portions protruding to the back surface of the substrate,
wherein the side passivation layer comprises a second upper portion protruding to the back surface of the substrate and spaced apart from the first upper portions in a horizontal direction, and
wherein the gap-fill dielectric layer fills a space between the first upper portions and the second upper portion.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the substrate of the semiconductor chip comprises a first material, and
wherein the side passivation layer comprises a second material, different from the first material.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the first material comprises silicon (Si) or a silicon compound, and
wherein the second material comprises at least one of silicon oxide (SiO), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN).

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the gap-fill dielectric layer comprises at least one of silicon oxide (SiO) and silicon nitride (SiN).

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein ends of the first upper portions of the through-electrodes are on a same level as, or higher than, an uppermost end of the second upper portion of the side passivation layer.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the ends of the first upper portions contact the back pads.

### Claim 7 (depends on 5)

The semiconductor package of claim 5, wherein the uppermost end of the second upper portion of the side passivation layer contacts the bonding dielectric layer.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the side passivation layer comprises a lower portion, opposite to the second upper portion, and
wherein the side passivation layer extends between the second upper portion and the lower portion.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein each of the bonding dielectric layer and the bonding insulating layer comprises at least one of silicon oxide (SiO) and silicon carbon nitride (SiCN).

### Claim 10 (depends on 1)

The semiconductor package of claim 1, further comprising:
first bump structures disposed in a region overlapping the semiconductor chip, and connected to the front pads; and
second bump structures disposed on opposite sides of the first bump structures.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, further comprising:
conductive posts penetrating through the gap-fill dielectric layer and the bonding dielectric layer, and connecting the connection pads of the top semiconductor chip and the second bump structures.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, further comprising:
bump structures below the semiconductor chip and the gap-fill dielectric layer; and
a redistribution structure electrically connecting the front pads and the bump structures.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the redistribution structure comprises:
an insulating material layer between the semiconductor chip and the bump structures; and
redistribution patterns within the insulating material layer and connecting the front pads and the bump structures.

### Claim 14 (depends on 12)

The semiconductor package of claim 12, wherein the side passivation layer comprises a lower portion contacting the redistribution structure, and
wherein the side passivation layer extends between the second upper portion and the lower portion.

### Claim 15

A semiconductor package comprising:
a semiconductor chip comprising:
a substrate comprising a front surface and a back surface opposite to the front surface;
front pads on the front surface;
through-electrodes electrically connected to the front pads and penetrating through the substrate and protruding to the back surface; and
back pads on the through-electrodes;
a side passivation layer surrounding the semiconductor chip;
a dielectric layer covering at least a portion of each of the semiconductor chip and the side passivation layer, and surrounding the through-electrodes and the back pads on the back surface of the substrate;
a top semiconductor chip on the dielectric layer, the top semiconductor chip comprising connection pads electrically connected to the back pads; and
bump structures below the semiconductor chip and connected to the front pads,
wherein the side passivation layer comprises an upper surface and a lower surface opposite to the upper surface,
wherein the upper surface of the side passivation layer and the back surface of the substrate extend in a same direction, and
wherein a first distance between the back surface of the substrate and a top surface of the dielectric layer is greater than a second distance between the upper surface of the side passivation layer and the top surface of the dielectric layer.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the semiconductor chip further comprises an insulating layer surrounding the front pads on the front surface of the substrate, and
wherein the lower surface of the side passivation layer is coplanar with a lower surface of the insulating layer, lower surfaces of the front pads, and a lower surface of the dielectric layer.

### Claim 17 (depends on 15)

The semiconductor package of claim 15, wherein the dielectric layer comprises:
a gap-fill dielectric layer contacting a side surface of the semiconductor chip and a side surface of each of the through-electrodes; and
a bonding dielectric layer on the gap-fill dielectric layer and contacting a side surface of each of the back pads.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein the top semiconductor chip further comprises a bonding insulating layer surrounding the connection pads and contacting the bonding dielectric layer, and
wherein each of the bonding dielectric layer and the bonding insulating layer comprises at least one of silicon oxide (SiO) and silicon carbon nitride (SiCN).

### Claim 19

A semiconductor package comprising:
a semiconductor chip comprising:
a substrate comprising a front surface and a back surface opposite to the front surface;
front pads on the front surface;
through-electrodes electrically connected to the front pads and penetrating through the substrate and protruding to the back surface; and
back pads disposed on the through-electrodes;
a side passivation layer surrounding the semiconductor chip and spaced from the through-electrodes in a horizontal direction;
a dielectric layer covering at least a portion of each of the semiconductor chip and the side passivation layer, and surrounding the through-electrodes and the back pads on the back surface of the substrate; and
a top semiconductor chip on the semiconductor chip and the dielectric layer, the top semiconductor chip comprising connection pads contacting the back pads.

### Claim 20 (depends on 19)

The semiconductor package of claim 19, wherein the side passivation layer extends in a direction intersecting the front surface and the back surface of the semiconductor chip.