Method of manufacturing semiconductor package including semiconductor chip having internal and external marks

A method for manufacturing a semiconductor package comprising:

• forming a first semiconductor chip having a first bonding surface, the first semiconductor chip including:
• a first outermost insulating layer providing the first bonding surface,
• a first internal insulating layer on the first outermost insulating layer,
• a first external marks within the first outermost insulating layer, and
• a first internal mark within the first internal insulating layer,
• wherein the first external marks include a first pattern having a first center portion and a second pattern having a first ring portion surrounding the first center portion when viewed in a plan view,
• wherein the first internal mark is disposed between the first center portion and the first ring portion when viewed in the plan view, and
• wherein the first external marks and the first internal mark together form a first alignment structure.

A method for manufacturing a semiconductor package comprising:

• forming a base wafer including a first alignment structure and a first external pad,
• wherein the first alignment structure includes first external marks including first concentric patterns having a first gap therebetween, and a first internal mark disposed in the first gap, and
• wherein the first alignment structure has a first projected planar shape when viewed in a plan view;
• forming a semiconductor chip including a second alignment structure and a second external pad,
• wherein the second alignment structure includes:
• second external marks including second concentric patterns having a second gap therebetween, and a second internal mark disposed in the second gap, and
• wherein the second alignment structure has a second projected planar shape when viewed in a plan view;
• and
• disposing the semiconductor chip on the base wafer so that the first alignment structure and the second alignment structure overlap each other.