# US 2026/0101752 A1 · Heat dissipation through redistribution structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101752 A1 - Document ID: US20260101752A1 - Status: Published application - Kind: A1 - Application number: 19/037,097 - Filed: 2025-01-25 - Published: 2026-04-09 - Earliest claimed: 2024-10-04 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Hsin-Yu Chen; Meng-Wei Chou; Jyun-Siang Peng; Yu-Hsiang Hu; Chien-Hsun Lee; Kathy Wei Yan - Web page: https://patentgrep.com/patent/US20260101752A1 ## CPC - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H05K 1/144: {Stacked arrangements of planar printed circuit boards} - H10D 80/20: the at least one device being covered by groups H10D1/00 - H10D48/00, e.g. assemblies comprising capacitors, power FETs or Schottky diodes - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H05K 1/181: associated with surface mounted components - H05K 2201/10378: Interposers - H05K 2201/10734: Ball grid array [BGA]; Bump grid array - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10D 80/30: the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips - H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) - H10W 90/00: Package configurations - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor package structure according to the present disclosure includes a substrate, an interposer bonded to the substrate by way of a plurality of first type solder features, and an integrated circuit (IC) die bonded to the interposer by way of a plurality of second type solder features. The interposer includes a redistribution structure and a seal ring structure extending around the redistribution structure. At least one of the plurality of second type solder features is electrically coupled to the seal ring structure. ## Claims ### Claim 1 A semiconductor package structure, comprising: a substrate; an interposer bonded to the substrate by way of a plurality of first type solder features, the interposer comprising: a redistribution structure, and a seal ring structure extending around the redistribution structure; and an integrated circuit (IC) die bonded to the interposer by way of a plurality of second type solder features, wherein at least one of the plurality of second type solder features is electrically coupled to the seal ring structure. ### Claim 2 (depends on 1) The semiconductor package structure of claim 1, wherein, within the interposer, the seal ring structure is electrically insulated from the redistribution structure. ### Claim 3 (depends on 1) The semiconductor package structure of claim 1, wherein the IC die comprises a plurality of transistors, wherein the at least one of the plurality of second type solder features electrically coupled to the seal ring structure is insulated from the plurality of transistors in the IC die. ### Claim 4 (depends on 3) The semiconductor package structure of claim 3, wherein the plurality of transistors in the IC die comprises multi-gate transistors. ### Claim 5 (depends on 1) The semiconductor package structure of claim 1, wherein the seal ring structure is electrically coupled to at least one of the plurality of first type solder features by way of a contact via. ### Claim 6 (depends on 1) The semiconductor package structure of claim 1, wherein the seal ring structure is electrically coupled to at least one of the plurality of first type solder features by way of a via ring, wherein the via ring extends continuously around a vertical projection area of the redistribution structure. ### Claim 7 (depends on 1) The semiconductor package structure of claim 1, wherein the seal ring structure comprises copper. ### Claim 8 (depends on 1) The semiconductor package structure of claim 1, wherein the substrate comprises a plurality of conductive features, wherein the seal ring structure is electrically insulated from the plurality of conductive features. ### Claim 9 A semiconductor package structure, comprising: a package substrate; an interposer bonded to the package substrate and comprising: a redistribution structure, and a seal ring structure extending around the redistribution structure; and an integrated circuit (IC) die bonded to the interposer by way of a plurality of first type solder features, wherein at least one of the plurality of first type solder features is electrically coupled to the seal ring structure. ### Claim 10 (depends on 9) The semiconductor package structure of claim 9, wherein the seal ring structure comprises metal lines and metal vias, wherein the metal lines and metal vias extend through an entire thickness of the interposer. ### Claim 11 (depends on 9) The semiconductor package structure of claim 9, wherein the IC die comprises a plurality of transistors, wherein the at least one of the plurality of first type solder features is electrically insulated from the plurality of transistors. ### Claim 12 (depends on 11) The semiconductor package structure of claim 11, wherein the interposer is bonded to the package structure by way of a plurality of second type solder features. ### Claim 13 (depends on 12) The semiconductor package structure of claim 12, wherein the seal ring structure is electrically coupled to at least one of the plurality of second type solder features by way of a contact via. ### Claim 14 (depends on 12) The semiconductor package structure of claim 12, wherein the seal ring structure is electrically coupled to the at least one of the plurality of second type solder features by way of a via ring, wherein the via ring extends continuously around a vertical projection area of the redistribution structure. ### Claim 15 (depends on 9) The semiconductor package structure of claim 9, wherein, within the interposer, the seal ring structure is insulated from the redistribution structure. ### Claim 16 A semiconductor package structure, comprising: a package substrate; an interposer bonded to the package substrate and comprising: a redistribution structure, and a seal ring structure extending around the redistribution structure; and an integrated circuit (IC) die comprising a plurality of transistors and bonded to the interposer by way of a plurality of contact features, wherein the plurality of contact features comprises a first subset of contact features and a second subset of contact features, wherein the first subset of contact features are electrically coupled to the plurality of transistors, wherein the second subset of contact features are electrically isolated from the plurality of transistors, wherein the second subset of contact features are electrically coupled to the seal ring structure. ### Claim 17 (depends on 16) The semiconductor package structure of claim 16, wherein the plurality of transistors in the IC die comprises multi-gate transistors. ### Claim 18 (depends on 16) The semiconductor package structure of claim 16, wherein the first subset of contact features is electrically coupled redistribution structure. ### Claim 19 (depends on 16) The semiconductor package structure of claim 16, wherein the interposer is bonded to the package substrate by way of a plurality of solder features, wherein the seal ring structure is bonded to the package substrate by way of at least one of the plurality of solder features. ### Claim 20 (depends on 19) The semiconductor package structure of claim 19, wherein the seal ring structure is electrically coupled to the at least one of the plurality of solder features by way of a plurality of contact vias.