# US 2026/0101744 A1 · Semiconductor package with bump structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101744 A1 - Document ID: US20260101744A1 - Status: Published application - Kind: A1 - Application number: 19/065,530 - Filed: 2025-02-27 - Published: 2026-04-09 - Earliest claimed: 2024-09-20 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Myoungsoo KIM; Jisung KIM; Seongsik MIN - Web page: https://patentgrep.com/patent/US20260101744A1 ## CPC - H10W 20/43: Layouts of interconnections - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10D 80/30: the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 70/611: {for connecting multiple chips together} - H10W 72/0198: {batch processes} - H10W 72/334: {Cross-sectional shape, i.e. in side view} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor package including: a base structure; a bump connected to the base structure; a chip connected to the bump; and a filling layer surrounding the bump, in which the chip includes: a substrate, an insulating structure between the substrate and the bump, a protective layer between the bump and the insulating structure, a conductive pad between the protective layer and the insulating structure, and a connection pattern penetrating the protective layer and connecting the bump and the conductive pad, and in which the filling layer comprises an interposed portion between the protective layer and the insulating structure. ## Claims ### Claim 1 A semiconductor package comprising: a base structure; a bump connected to the base structure; a chip connected to the bump; and a filling layer surrounding the bump, wherein the chip comprises: a substrate, an insulating structure between the substrate and the bump, a protective layer between the bump and the insulating structure, a conductive pad between the protective layer and the insulating structure, and a connection pattern penetrating the protective layer and connecting the bump and the conductive pad, and wherein the filling layer comprises an interposed portion between the protective layer and the insulating structure. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the insulating structure comprises a surface in contact with a first surface of the interposed portion, and wherein the protective layer comprises a surface in contact with a second surface of the interposed portion. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the insulating structure comprises a sidewall in contact with a sidewall of the interposed portion. ### Claim 4 (depends on 2) The semiconductor package of claim 2, wherein the protective layer comprises a sidewall in contact with a sidewall of the interposed portion. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the protective layer comprises (i) a first portion in contact with the insulating structure and (ii) a second portion spaced apart from the insulating structure, and wherein the interposed portion is interposed between the second portion of the protective layer and the insulating structure. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein the second portion of the protective layer is at a level below the first portion of the protective layer. ### Claim 7 (depends on 6) The semiconductor package of claim 6, wherein a sidewall of the interposed portion is in contact with a sidewall of the first portion of the protective layer, and a surface of the interposed portion is in contact with a surface of the second portion of the protective layer. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the interposed portion is at a same level as the conductive pad. ### Claim 9 A semiconductor package comprising: a base structure; a bump connected to the base structure; and a chip connected to the bump, wherein the chip comprises: a substrate, an insulating structure between the substrate and the bump, a protective layer between the bump and the insulating structure, a conductive pad between the protective layer and the insulating structure, and a connection pattern penetrating the protective layer and connecting the bump and the conductive pad, wherein the protective layer comprises a first portion, and a second portion and a third portion spaced apart from each other with the first portion therebetween, wherein a surface of the first portion of the protective layer is in contact with a surface of the insulating structure, wherein a surface of the third portion of the protective layer is in contact with a surface of the conductive pad, and wherein a surface of the second portion of the protective layer is spaced apart from the insulating structure and the conductive pad. ### Claim 10 (depends on 9) The semiconductor package of claim 9, wherein a first distance between the second portion of the protective layer and a sidewall of the chip is smaller than a second distance between the third portion of the protective layer and the sidewall of the chip. ### Claim 11 (depends on 9) The semiconductor package of claim 9, further comprising a filling layer surrounding the bump, wherein the filling layer comprises a first interposed portion between the second portion of the protective layer and the insulating structure. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the chip further comprises a conductive via in contact with the first interposed portion, and a surface of the conductive via is coplanar with the surface of the insulating structure. ### Claim 13 (depends on 11) The semiconductor package of claim 11, wherein the insulating structure comprises: a first insulating layer in contact with the protective layer; and a second insulating layer in contact with the first insulating layer and spaced apart from the protective layer, and the filling layer further comprises a second interposed portion between the first insulating layer and the second insulating layer. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein the first insulating layer comprises: a surface in contact with a surface of the second interposed portion; and a sidewall connected to the surface of the first insulating layer, and the sidewall of the first insulating layer is inclined with respect to the surface of the insulating structure. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the protective layer comprises a sidewall that is coplanar with the sidewall of the first insulating layer, and the sidewall of the protective layer is inclined with respect to the surface of the insulating structure. ### Claim 16 A semiconductor package comprising: a base structure; a bump connected to the base structure; a chip connected to the bump; and a filling layer surrounding the bump, wherein the chip comprises: a substrate, an insulating structure between the substrate and the bump, a semiconductor device between the substrate and the insulating structure, a conductive via connected to the semiconductor device, a conductive pad in contact with the conductive via, a protective layer in contact with the insulating structure and the conductive pad, and a connection pattern penetrating the protective layer and in contact with the bump and the conductive pad, wherein the protective layer comprises a first portion in contact with a surface of the insulating structure and a second portion spaced apart from the insulating structure, and wherein the filling layer comprises: a first interposed portion in contact with a surface of the second portion of the protective layer, and a first connection portion in contact with a sidewall of the second portion of the protective layer. ### Claim 17 (depends on 16) The semiconductor package of claim 16, wherein a width of the protective layer is smaller than a width of the insulating structure. ### Claim 18 (depends on 16) The semiconductor package of claim 16, wherein the insulating structure comprises: a first insulating layer in contact with the protective layer; and a second insulating layer in contact with the first insulating layer and spaced apart from the protective layer, and wherein the filling layer further comprises: a second interposed portion between the first insulating layer and the second insulating layer, and a second connection portion in contact with a sidewall of the first insulating layer and a sidewall of the protective layer. ### Claim 19 (depends on 18) The semiconductor package of claim 18, wherein a surface of the second interposed portion is in contact with the second insulating layer, and a surface of the second interposed portion is in contact with the first insulating layer. ### Claim 20 (depends on 18) The semiconductor package of claim 18, wherein a first distance between the second interposed portion and the substrate is smaller than a second distance between the first interposed portion and the substrate.