# US 2026/0101736 A1 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101736 A1 - Document ID: US20260101736A1 - Status: Published application - Kind: A1 - Application number: 19/082,715 - Filed: 2025-03-18 - Published: 2026-04-09 - Earliest claimed: 2024-09-25 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yubin SONG; Pilkyu KANG; Jaewha PARK - Web page: https://patentgrep.com/patent/US20260101736A1 ## CPC - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 70/68: Shapes or dispositions thereof - H10W 90/00: Package configurations - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package may include: a first semiconductor chip including a first substrate including a first front surface opposite to a first rear surface, first front pads on the first front surface, first through-electrodes electrically connected to the first front pads, and first rear pads on the first through-electrodes, the first through-electrodes penetrating the first substrate and protruding to the first rear surface; a first step structure including a first dummy substrate, a first buffer layer on the first dummy substrate, and a first cavity penetrating the first dummy substrate and the first buffer layer, with the first semiconductor chip in the first cavity; and a first dielectric layer on at least portions of the first semiconductor chip and the first step structure, and around the first through-electrodes and the first rear pads on the first rear surface of the first substrate. ## Claims ### Claim 1 A semiconductor package, comprising: a first semiconductor chip comprising a first substrate comprising a first front surface opposite to a first rear surface, first front pads on the first front surface, first through-electrodes electrically connected to the first front pads, and first rear pads on the first through-electrodes, the first through-electrodes penetrating the first substrate and protruding to the first rear surface; a first step structure comprising a first dummy substrate, a first buffer layer on the first dummy substrate, and a first cavity penetrating the first dummy substrate and the first buffer layer, with the first semiconductor chip in the first cavity; a first dielectric layer on at least portions of the first semiconductor chip and the first step structure, and around the first through-electrodes and the first rear pads on the first rear surface of the first substrate; a top semiconductor chip on the first dielectric layer and comprising connection pads electrically connected to the first rear pads; and bump structures below the first semiconductor chip and connected to the first front pads, wherein the first step structure has a first surface of the first dummy substrate facing in a same direction as the first front surface of the first substrate, and a second surface of the first buffer layer facing in a same direction as the first rear surface of the first substrate, and wherein a first distance between the first rear surface of the first substrate and an uppermost surface of the first dielectric layer is greater than a second distance between the second surface of the first step structure and the uppermost surface of the first dielectric layer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first substrate of the first semiconductor chip, and the first dummy substrate of the first step structure comprise a first material, and wherein the first buffer layer of the first step structure comprises a second material different from the first material. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the first material comprises silicon (Si) or a silicon compound, and wherein the second material comprises at least one of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein an upper end of the first through-electrodes in contact with the first rear pads is at a same level as or higher than a level of the second surface of the first step structure. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the first dielectric layer comprises a first gap-fill dielectric layer in contact with a side surface of the first semiconductor chip and side surfaces of the first through-electrodes, and a first bonding dielectric layer on the first gap-fill dielectric layer and in contact with side surfaces of the first rear pads. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein the top semiconductor chip further comprises a bonding insulating layer in contact with the first bonding dielectric layer, the bonding insulating layer being around the connection pads, and wherein the first bonding dielectric layer and the bonding insulating layer comprise at least one of silicon oxide (SiO), or silicon carbon nitride (SiCN). ### Claim 7 (depends on 5) The semiconductor package of claim 5, wherein at least a portion of the first bonding dielectric layer is in contact with the second surface of the first step structure. ### Claim 8 (depends on 1) The semiconductor package of claim 1, further comprising: a buffer insulating layer between the first dielectric layer and the first step structure, and between the first dielectric layer and the first semiconductor chip. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the buffer insulating layer comprises at least one of silicon oxide (SiO) or silicon nitride (SiN). ### Claim 10 (depends on 1) The semiconductor package of claim 1, further comprising: at least one reconfigured structure between the first semiconductor chip and the top semiconductor chip, wherein the at least one reconfigured structure comprises: a second semiconductor chip comprising a second substrate comprising a second front surface facing the top semiconductor chip and a second rear surface facing the first semiconductor chip, second front pads on the second front surface, second through-electrodes electrically connected to the second front pads, and second rear pads on the second through-electrodes, the second through-electrodes penetrating the second substrate and protruding to the second rear surface, a second step structure comprising a second dummy substrate, a second buffer layer on the second dummy substrate, and a second cavity penetrating the second dummy substrate and the second buffer layer, with the second semiconductor chip in the second cavity, and a second dielectric layer on at least portions of the second semiconductor chip and the second step structure and around the second through-electrodes and the second rear pads on the second rear surface of the second substrate. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the second step structure has a third surface of the second dummy substrate facing in a same direction as the second front surface of the second, and a fourth surface of the second buffer layer facing in a same direction as the second rear surface of the second substrate, and wherein a third distance between the second rear surface of the second substrate and a lowermost surface of the second dielectric layer is greater than a fourth distance between the fourth surface of the second step structure and a lowermost surface of the second dielectric layer. ### Claim 12 (depends on 10) The semiconductor package of claim 10, wherein the second front pads are in contact with the connection pads of the top semiconductor chip, and wherein the second rear pads are in contact with the first rear pads of the first semiconductor chip. ### Claim 13 (depends on 10) The semiconductor package of claim 10, wherein the second semiconductor chip further comprises an insulating layer around the second front pads, wherein the top semiconductor chip further comprises a bonding insulating layer around the connection pads and in contact with the insulating layer of the second semiconductor chip, and wherein the insulating layer and the bonding insulating layer comprise at least one of silicon oxide (SiO), or silicon carbon nitride (SiCN). ### Claim 14 (depends on 10) The semiconductor package of claim 10, wherein the first dielectric layer comprises a first bonding dielectric layer around side surfaces of the first rear pads, and wherein the second dielectric layer comprises a second gap-fill dielectric layer in contact with side surfaces of the second semiconductor chip and the second through-electrodes, and a second bonding dielectric layer on the second gap-fill dielectric layer and in contact with side surfaces of the second rear pads. ### Claim 15 (depends on 14) The semiconductor package of claim 14, wherein the first bonding dielectric layer is in contact with the second bonding dielectric layer, and wherein the first bonding dielectric layer and the second bonding dielectric layer comprise at least one of silicon oxide (SiO), or silicon carbon nitride (SiCN). ### Claim 16 (depends on 1) The semiconductor package of claim 1, further comprising: conductive posts penetrating the first step structure and connecting the connection pads of the top semiconductor chip to the bump structures. ### Claim 17 (depends on 1) The semiconductor package of claim 1, further comprising: a redistribution structure between the first semiconductor chip and the bump structures, and comprising redistribution patterns electrically connecting the first front pads to the bump structures. ### Claim 18 A semiconductor package, comprising: a semiconductor chip comprising a substrate comprising a front surface opposite to a rear surface, front pads on the front surface, through-electrodes electrically connected to the front pads, and rear pads on the through-electrodes, the through-electrodes penetrating the substrate and protruding to the rear surface; a step structure comprising a dummy substrate, a buffer layer on the dummy substrate, and a cavity penetrating the dummy substrate and the buffer layer, with the semiconductor chip in the cavity; and a dielectric layer on at least portions of the semiconductor chip and the step structure, and around the through-electrodes and the rear pads on the rear surface of the substrate, wherein the substrate and the dummy substrate comprise a first material, and wherein the buffer layer comprises a second material different from the first material. ### Claim 19 (depends on 18) The semiconductor package of claim 18, wherein the first material comprises a semiconductor material, and wherein the second material comprises at least one of an oxide or a nitride of the semiconductor material. ### Claim 20 A semiconductor package, comprising: a semiconductor chip comprising a substrate comprising a front surface opposite to a rear surface, front pads on the front surface, through-electrodes electrically connected to the front pads, and rear pads on the through-electrodes, the through-electrodes penetrating the substrate and protruding to the rear surface; a step structure around the semiconductor chip and comprising a lower surface opposite to an upper surface; a gap-fill dielectric layer on the rear surface of the semiconductor chip, and the upper surface of the step structure; a bonding dielectric layer on the gap-fill dielectric layer and on at least portions of the rear pads; and a top semiconductor chip on the semiconductor chip, and comprising connection pads in contact with the rear pads, and a bonding insulating layer on at least portions of the connection pads and in contact with the bonding dielectric layer, wherein an upper surface of the gap-fill dielectric layer and upper ends of the through-electrodes provide a flat surface with the bonding dielectric layer and the rear pads on the flat surface, and wherein the step structure comprises a buffer layer adjacent to the flat surface.