# US 2026/0101733 A1 · Semiconductor element and manufacturing method thereof

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- Number: US 2026/0101733 A1
- Document ID: US20260101733A1
- Status: Published application
- Kind: A1
- Application number: 19/225,805
- Filed: 2025-06-02
- Published: 2026-04-09
- Earliest claimed: 2024-10-08
- Assignees: National Cheng Kung University
- Applicants: National Cheng Kung University
- Inventors: Wei-Chen TU; Yi-Hsiang SHIH
- Web page: https://patentgrep.com/patent/US20260101733A1

## CPC

- H10W 20/064: {by modifying the conductivity of conductive parts, e.g. by alloying}
- H10W 20/4462: {Carbon or carbon-containing materials, e.g. graphene}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor element includes a preparation step, a protective gas introduction step, a reaction gas introduction step, and a deposition step. Firstly, a semiconductor sample is prepared on a stage of a cavity, where a line width of a circuit pattern layer of the semiconductor sample is less than 100 nm. Then, the stage is heated to and maintained at 250° C. to 480° C., and plasma is activated in a protective atmosphere to crack introduced benzene vapor to form a graphene layer on the circuit pattern layer, where a thickness of the graphene layer is 0.3 nm to 4.5 nm. The reaction can be carried out at a low temperature using the benzene vapor as a carbon source, improving properties of graphene deposited on a surface of the circuit pattern layer, and greatly reducing resistance of the circuit pattern layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor element, comprising:
a preparation step: preparing a semiconductor sample and placing the semiconductor sample on a stage of a cavity, wherein the semiconductor sample comprises a semiconductor substrate and a circuit pattern layer, the circuit pattern layer is on the semiconductor substrate, and a line width of the circuit pattern layer is less than 100 nm;
a protective gas introduction step: vacuumizing the cavity, introducing a protective gas, and heating the stage to 250° C. to 480° C.;
a reaction gas introduction step: stopping introducing the protective gas, introducing a reaction gas, and maintaining a temperature of the stage at 250° C. to 480° C., wherein the reaction gas comprises a hydrogen gas and benzene vapor; and
a deposition step: reintroducing the protective gas, activating plasma, and maintaining the temperature of the stage at 250° C. to 480° C., so that the benzene vapor cracks to form a graphene layer on the circuit pattern layer, wherein a thickness of the graphene layer is 0.3 nm to 4.5 nm.

### Claim 2 (depends on 1)

The method for manufacturing the semiconductor element according to claim 1, wherein a material of the circuit pattern layer is selected from the group consisting of copper, nickel, aluminum, and an alloy thereof.

### Claim 3 (depends on 1)

The method for manufacturing the semiconductor element according to claim 1, wherein the line width of the circuit pattern layer is less than 60 nm.

### Claim 4 (depends on 1)

The method for manufacturing the semiconductor element according to claim 1, wherein the thickness of the graphene layer is 0.3 nm to 3 nm.

### Claim 5 (depends on 1)

The method for manufacturing the semiconductor element according to claim 1, wherein in the protective gas introduction step, the reaction gas introduction step, and the deposition step, the temperature of the stage is maintained at 300° C. to 400° C.

### Claim 6 (depends on 1)

The method for manufacturing the semiconductor element according to claim 1, wherein in the deposition step, a flow rate of the introduced protective gas is 10 sccm to 75 sccm, and a flow rate of the introduced reaction gas is less than 15 sccm.

### Claim 7

A semiconductor element, comprising:
a semiconductor substrate;
a circuit pattern layer on the semiconductor substrate, wherein a line width of the circuit pattern layer is less than 100 nm; and
a graphene layer on a surface of the circuit pattern layer, wherein a thickness of the graphene layer is 0.3 nm to 4.5 nm.

### Claim 8 (depends on 7)

The semiconductor element according to claim 7, wherein a material of the circuit pattern layer is selected from the group consisting of copper, nickel, aluminum, and an alloy thereof.

### Claim 9 (depends on 7)

The semiconductor element according to claim 7, wherein the line width of the circuit pattern layer is less than 60 nm.

### Claim 10 (depends on 7)

The semiconductor element according to claim 7, wherein the thickness of the graphene layer is 0.3 nm to 3 nm.