# US 2026/0101720 A1 · Semiconductor package and manufacturing method thereof

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- Number: US 2026/0101720 A1
- Document ID: US20260101720A1
- Status: Published application
- Kind: A1
- Application number: 19/274,982
- Filed: 2025-07-21
- Published: 2026-04-09
- Earliest claimed: 2024-09-25
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyoung-Min LEE; Sang-Hoon JUNG
- Web page: https://patentgrep.com/patent/US20260101720A1

## CPC

- H10P 74/20: characterised by the properties tested or measured, e.g. structural or electrical properties
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 20/43: Layouts of interconnections
- H10W 90/00: Package configurations
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/301: {for alignment}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/722: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first semiconductor chip including: a first substrate, a first wiring layer on a first surface of the first substrate, a plurality of first dummy pads electrically connected to each other by a redistribution layer disposed between the first wiring layer and a first passivation layer, and a plurality of second dummy pads disposed adjacent to the plurality of first dummy pads on the first wiring layer; and a second semiconductor chip including: a second substrate, a second wiring layer on the second substrate and opposite to the first surface of the first substrate, a plurality of third dummy pads having at least a portion that overlaps the plurality of first dummy pads on the second wiring layer, and a plurality of power pads arranged adjacent to the plurality of third dummy pads and configured to provide a test voltage.

## Claims

### Claim 1

A semiconductor package comprising:
a first semiconductor chip comprising:
a first substrate,
a first wiring layer on a first surface of the first substrate,
a plurality of first dummy pads electrically connected to each other by a redistribution layer disposed between the first wiring layer and a first passivation layer, and
a plurality of second dummy pads disposed adjacent to the plurality of first dummy pads on the first wiring layer, wherein each second dummy pad of the plurality of second dummy pads is floated; and
a second semiconductor chip comprising:
a second substrate,
a second wiring layer on the second substrate and opposite to the first surface of the first substrate,
a plurality of third dummy pads having at least a portion that overlaps the plurality of first dummy pads on the second wiring layer, and
a plurality of power pads arranged adjacent to the plurality of third dummy pads and configured to provide a test voltage.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein:
the plurality of second dummy pads are electrically isolated from a first wiring structure in the first wiring layer, and
the plurality of third dummy pads are electrically isolated from a second wiring structure within the second wiring layer.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein:
the plurality of first dummy pads and the redistribution layer are electrically isolated from the first wiring structure.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein:
the plurality of power pads comprise a plurality of first power pads configured to provide the test voltage and a plurality of second power pads configured to provide a ground voltage.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein:
one or more of the plurality of first power pads and one or more of the plurality of second power pads are alternately arranged along a first direction on the first surface of the first substrate.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein:
the plurality of power pads are electrically connected to the second wiring structure within the second wiring layer.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein:
the second substrate comprises a second surface facing the first surface of the first substrate and a third surface opposite the second surface,
the second semiconductor chip further comprises a test pad on the third surface and electrically connected to the plurality of power pads.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, further comprising:
a substrate facing the third surface,
wherein the second semiconductor chip and the substrate are bonded via a bump.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein:
the plurality of first dummy pads are arranged in an L shape on the first surface,
the redistribution layer is arranged in an L shape between the first surface and the plurality of first dummy pads, and
the plurality of first dummy pads are in contact with the redistribution layer.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein:
the plurality of first dummy pads are arranged in a bar shape including at least two columns on the first surface,
the redistribution layer is arranged in a bar shape between the first surface and the plurality of first dummy pads, and
the plurality of first dummy pads are in contact with the redistribution layer.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, wherein:
the plurality of first dummy pads and the plurality of third dummy pads are electrically connected through a conductive bump.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, wherein:
one or more of the plurality of first dummy pads and one or more of the plurality of third dummy pads are in contact with each other.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein:
the first semiconductor chip further comprises the first passivation layer that does not cover one or more of the plurality of first dummy pads and does not cover one or more of the plurality of second dummy pads,
the second semiconductor chip further comprises a second passivation layer that does not cover one or more of the plurality of third dummy pads and one or more of the plurality of power pads, and
at least a portion of the first passivation layer and at least a portion of the second passivation layer are in contact with each other.

### Claim 14

A semiconductor package comprising
a first semiconductor chip comprising:
a first normal region overlapping in a plane a center of a first surface of a first substrate,
a plurality of signal power pads,
a first test region overlapping edges of the first surface,
a plurality of first dummy pads electrically connected to each other,
a plurality of second dummy pads positioned adjacent to the plurality of first dummy pads, wherein each second dummy pad of the plurality of second dummy pads is floated, and
a first alignment key positioned adjacent to the plurality of first dummy pads and the plurality of second dummy pads; and
a second semiconductor chip comprising:
a second test region overlapping the first test region with at least a portion on a second surface of a second substrate facing the first surface of the first substrate,
a plurality of power pads having at least a part that overlaps the plurality of second dummy pads and configured to provide a test voltage, and
a second alignment key corresponding to the first alignment key.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein:
the second test region further comprises a plurality of third dummy pads disposed overlapping the plurality of first dummy pads with at least a part on the second surface, wherein each third dummy pad from the plurality of third dummy pads is floated.

### Claim 16 (depends on 14)

The semiconductor package of claim 14, further comprising:
a third semiconductor chip that does not overlap the first semiconductor chip on the second surface of the second substrate,
wherein the third semiconductor chip further comprises a second normal region corresponding to the first normal region and a third test region corresponding to the first test region.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein:
the second semiconductor chip further comprises a fourth test region having at least a part that overlaps the third test region.

### Claim 18

A manufacturing method of a semiconductor package comprising:
bonding a first semiconductor chip onto a first surface of a second semiconductor chip at a wafer level using an alignment key;
providing a test signal to the second semiconductor chip using a test pad arranged on a second surface of the second semiconductor chip opposite to the first surface of the second semiconductor chip;
testing an alignment of a stacking structure including the first semiconductor chip and the second semiconductor chip by detecting a current corresponding to the test signal at the test pad; and
sawing a wafer including the second semiconductor chip.

### Claim 19 (depends on 18)

The manufacturing method of the semiconductor package of claim 18, wherein:
the test signal includes a test voltage and a ground voltage,
providing the test signal further comprises providing the test voltage and the ground voltage to the test pad through a probe pin, and
testing the alignment further comprises detecting the current corresponding to the test signal through the probe pin.

### Claim 20 (depends on 19)

The manufacturing method of the semiconductor package of claim 19, further comprising:
determining the stacking structure as a non-defective product in response to the current not being detected in the testing of the alignment.