# US 2026/0101682 A1 · Selective deposition method of thin film and method of manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101682 A1 - Document ID: US20260101682A1 - Status: Published application - Kind: A1 - Application number: 19/349,960 - Filed: 2025-10-04 - Published: 2026-04-09 - Earliest claimed: 2024-10-04 - Assignees: Samsung Electronics Co., Ltd.; Incheon National University Research & Business Foundation; Hongik University Industry-Academia Cooperation Foundation - Applicants: Samsung Electronics Co., Ltd; Incheon National University Research & Business Foundation; Hongik University Industry-Academia Cooperation Foundation - Inventors: Young Min LEE; Han-Bo-Ram LEE; Miso KIM; Bonggeun SHONG; JEONGYUB LEE; Youngchul LEEM; Eun-Hyoung CHO; Dabin KONG - Web page: https://patentgrep.com/patent/US20260101682A1 ## CPC - H10P 14/432: {using selective deposition} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A selective deposition method of a thin film includes: exposing a plurality of dielectric areas including a first dielectric area and a second dielectric area, supplying a reaction inhibitor and adsorbing the reaction inhibitor onto the plurality of dielectric areas, supplying a reaction auxiliary agent, which reacts with the reaction inhibitor, to selectively remove the reaction inhibitor adsorbed on the first dielectric area, supplying a reaction precursor for forming the thin film and adsorbing the reaction precursor for forming the thin film on the first dielectric area from which the reaction inhibitor is removed, and supplying a reactant for forming the thin film, which reacts with the a reaction precursor for forming the thin film, to selectively form an atomic layer on the first dielectric area. ## Claims ### Claim 1 A selective deposition method of a thin film, the selective deposition method comprising: exposing a plurality of dielectric areas including a first dielectric area and a second dielectric area; supplying a reaction inhibitor to adsorb the reaction inhibitor onto the plurality of dielectric areas; supplying a reaction auxiliary agent, which reacts with the reaction inhibitor, to selectively remove the reaction inhibitor adsorbed on the first dielectric area; supplying a reaction precursor for forming the thin film to adsorb the reaction precursor on the first dielectric area from which the reaction inhibitor is removed; and supplying a reactant for forming the thin film, which reacts with the reaction precursor, to selectively form an atomic layer on the first dielectric area. ### Claim 2 (depends on 1) The selective deposition method of claim 1, wherein the first dielectric area comprises a first dielectric, the second dielectric area comprises a second dielectric different from the first dielectric, and the first dielectric and the second dielectric have different activation energies to remove the reaction inhibitor by the reaction auxiliary agent. ### Claim 3 (depends on 2) The selective deposition method of claim 2, wherein an activation energy of the first dielectric to remove the reaction inhibitor is less than an activation energy of the second dielectric to remove the reaction inhibitor. ### Claim 4 (depends on 2) The selective deposition method of claim 2, wherein the first dielectric and the second dielectric are each independently an oxide or an oxynitride, or the first dielectric and the second dielectric are each independently a nitride or an oxynitride. ### Claim 5 (depends on 4) The selective deposition method of claim 4, wherein the first dielectric and the second dielectric are each independently an oxide, a nitride, or an oxynitride, each including Ag, Mg, Cu, Zr, Zn, Hf, Cr, Al, Co, Fe, Ti, Sn, Si, Ge, Mn, W, Mo, or a combination thereof. ### Claim 6 (depends on 5) The selective deposition method of claim 5, wherein the first dielectric is an oxide including Ag, Mg, Cu, Zr, Zn, Hf, Cr, Al, Co, Fe, Ti, Sn, or a combination thereof or an oxynitride including Ag, Mg, Cu, Zr, Zn, Hf, Cr, Al, Co, Fe, Ti, Sn or a combination thereof, and the second dielectric is an oxide including Si, Ge, Mn, W, Mo, or a combination thereof or an oxynitride including Si, Ge, Mn, W, Mo, or a combination thereof. ### Claim 7 (depends on 2) The selective deposition method of claim 2, wherein the plurality of dielectric areas further comprise a third dielectric area, the third dielectric area comprises a third dielectric which is different from the first dielectric and the second dielectric, and an activation energy of the third dielectric to remove the reaction inhibitor is greater than an activation energy of the first dielectric to remove the reaction inhibitor and is less than an activation energy of the second dielectric to remove the reaction inhibitor. ### Claim 8 (depends on 7) The selective deposition method of claim 7, wherein the first dielectric is an oxide including Ag, Mg, Cu, Zr, Zn, Hf, Cr, Al, Co, Fe, or a combination thereof or an oxynitride including Ag, Mg, Cu, Zr, Zn, Hf, Cr, Al, Co, Fe, or a combination thereof, the second dielectric is an oxide including Si, Ge, Mn, W, Mo, or a combination thereof or an oxynitride including Si, Ge, Mn, W, Mo, or a combination thereof, and the third dielectric is an oxide Sn, Ti, or a combination thereof or an oxynitride including Sn, Ti, or a combination thereof. ### Claim 9 (depends on 7) The selective deposition method of claim 7, wherein in the supplying of the reaction auxiliary agent, a portion of the reaction inhibitor adsorbed on the third dielectric area is removed, and the reaction inhibitor remaining on the third dielectric area is less than the reaction inhibitor remaining on the second dielectric area. ### Claim 10 (depends on 7) The selective deposition method of claim 7, wherein in the supplying of the reactant, the thin film is formed on the first dielectric area and the third dielectric area, the thin film on the first dielectric area is formed to have a first thickness, and the thin film on the third dielectric area is formed to have a second thickness thinner than the first thickness. ### Claim 11 (depends on 1) The selective deposition method of claim 1, wherein the reaction inhibitor comprises dimethylamino trimethylsilane, dimethylamino dimethylsilane, diethylamino trimethylsilane, diethylamino dimethylsilane, or a combination thereof. ### Claim 12 (depends on 1) The selective deposition method of claim 1, wherein the reaction auxiliary agent comprises H2O, H2O2, NH3, H2, or a combination thereof. ### Claim 13 (depends on 1) The selective deposition method of claim 1, wherein the thin film comprises a conductive layer including one or more atomic layers. ### Claim 14 (depends on 13) The selective deposition method of claim 13, wherein the conductive layer comprises Cu, Al, Ti, Ta, W, Co, Mo, Ni, Ag, Au, Pt, Ir, Re, Rh, Ru, an alloy thereof, a nitride thereof, a carbide thereof, or a combination thereof. ### Claim 15 (depends on 1) The selective deposition method of claim 1, wherein the first dielectric area and the second dielectric area have a three-dimensional surface, respectively, and the thin film is selectively formed on the three-dimensional surface of the first dielectric area. ### Claim 16 (depends on 1) A method for manufacturing a semiconductor device, the method comprising: forming a dielectric layer; and selectively depositing one or more atomic layers on the dielectric layer, wherein the depositing of the one or more atomic layers comprises the selective deposition method of the thin film of claim 1. ### Claim 17 (depends on 1) A method for manufacturing a semiconductor device, the method comprising: forming a transistor channel on a substrate; forming a gate dielectric layer on the transistor channel; and forming a gate electrode on the gate dielectric layer, wherein the forming of the gate electrode comprises the selective deposition method of the thin film of claim 1. ### Claim 18 A method of manufacturing a semiconductor device, the method comprising: forming a transistor channel on a substrate; forming a gate dielectric layer on the transistor channel; and forming a gate electrode on the gate dielectric layer, wherein the transistor channel comprises a first transistor channel and a second transistor channel which are stacked in a vertical direction with respect to a surface of the substrate, the gate electrode comprises a first gate electrode and a second gate electrode which are stacked in the vertical direction with respect to the surface of the substrate and comprise different conductors, the first gate electrode overlaps the first transistor channel in the vertical direction, and the second gate electrode overlaps the second transistor channel in the vertical direction, and the forming of the gate electrode comprises forming a conductor for the first gate electrode on the gate dielectric layer, forming a hardmask layer on the conductor for the first gate electrode, removing a portion of the hardmask layer to expose a portion of the conductor for the first gate electrode, removing an exposed portion of the conductor for the first gate electrode and exposing a portion of the gate dielectric layer, supplying a reaction inhibitor onto an exposed portion of the gate dielectric layer and the hardmask layer to adsorb the reaction inhibitor onto the exposed portion of the gate dielectric layer and the hardmask layer, supplying a reaction auxiliary agent, which reacts with the reaction inhibitor, to selectively remove the reaction inhibitor adsorbed on the exposed portion of the gate dielectric layer, supplying a reaction precursor for a second gate electrode to adsorb the reaction precursor for the second gate electrode on a portion of the gate dielectric layer from which the reaction inhibitor is removed, supplying a reactant for the second gate electrode, which reacts with the reactant precursor for the second gate electrode, to selectively form the second gate electrode on the gate dielectric layer, and removing the hardmask layer. ### Claim 19 (depends on 18) The method of claim 18, further comprising forming a conductive layer having a different work function from the second gate electrode after the removing of the hardmask layer. ### Claim 20 (depends on 18) The method of claim 18, wherein the gate dielectric layer comprises an oxide including Ag, Mg, Cu, Zr, Zn, Hf, Cr, Al, Co, Fe, Ti, Sn, or a combination thereof or an oxynitride including Ag, Mg, Cu, Zr, Zn, Hf, Cr, Al, Co, Fe, Ti, Sn, or a combination thereof, the hardmask layer comprises an oxide including Si, Ge, Mn, W, Mo, or a combination thereof or an oxynitride including Si, Ge, Mn, W, Mo, or a combination thereof.