# US 2026/0101577 A1 · Semiconductor device structure and methods of forming the same

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- Number: US 2026/0101577 A1
- Document ID: US20260101577A1
- Status: Published application
- Kind: A1
- Application number: 19/047,694
- Filed: 2025-02-07
- Published: 2026-04-09
- Earliest claimed: 2024-10-06
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Guan-Lin CHEN; Chun Yi CHOU; Kuo-Cheng CHIANG; Shi Ning JU; Chih-Hao WANG
- Web page: https://patentgrep.com/patent/US20260101577A1

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/502: {characterised by the stacked channels}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Embodiments of the present disclosure provide a semiconductor device structure and methods for forming the same. The structure includes a first semiconductor layer disposed in a first region and a second semiconductor layer surrounding the first semiconductor layer in the first region. The first and second semiconductor layers comprise different materials. The structure further includes a first gate electrode layer surrounding a portion of the second semiconductor layer, a first source/drain region electrically connected to the second semiconductor layer, and a second source/drain region electrically connected to the second semiconductor layer. The second semiconductor layer is disposed between the first and second source/drain regions.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a first semiconductor layer disposed in a first region;
a second semiconductor layer surrounding the first semiconductor layer in the first region, wherein the first and second semiconductor layers comprise different materials;
a first gate electrode layer surrounding a portion of the second semiconductor layer;
a first source/drain region electrically connected to the second semiconductor layer; and
a second source/drain region electrically connected to the second semiconductor layer, wherein the second semiconductor layer is disposed between the first and second source/drain regions.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, further comprising an interfacial layer disposed between the second semiconductor layer and the first gate electrode layer and a gate dielectric layer disposed between the interfacial layer and the first gate electrode layer.

### Claim 3 (depends on 2)

The semiconductor device structure of claim 2, wherein the interfacial layer surrounds the first and second semiconductor layers.

### Claim 4 (depends on 2)

The semiconductor device structure of claim 2, further comprising a first dielectric spacer disposed between the first source/drain region and the first gate electrode layer and a second dielectric spacer disposed between the second source/drain region and the first gate electrode layer.

### Claim 5 (depends on 1)

The semiconductor device structure of claim 1, further comprising a third semiconductor layer disposed on a substrate portion, wherein the first and second source/drain regions are disposed on the third semiconductor layer.

### Claim 6 (depends on 1)

The semiconductor device structure of claim 1, wherein the first semiconductor layer comprises Si, and the second semiconductor layer comprises SiGe.

### Claim 7 (depends on 6)

The semiconductor device structure of claim 6, wherein the second semiconductor layer has about five atomic percent to about 60 atomic percent of germanium.

### Claim 8 (depends on 1)

The semiconductor device structure of claim 1, further comprising a fourth semiconductor layer disposed in a second region and a second gate electrode layer surrounding a portion of the fourth semiconductor layer.

### Claim 9 (depends on 8)

The semiconductor device structure of claim 8, wherein the first region is a PMOS region, and the second region is an NMOS region.

### Claim 10

A semiconductor device structure, comprising:
a first semiconductor layer disposed over a substrate portion;
a second semiconductor layer disposed on the substrate portion below the first semiconductor layer, wherein the first and second semiconductor layers comprise a same material, and the second semiconductor layer and the substrate portion comprise different materials;
a first source/drain region disposed on the second semiconductor layer; and
a second source/drain region disposed on the second semiconductor layer, wherein the first semiconductor layer is disposed between the first and second source/drain regions.

### Claim 11 (depends on 10)

The semiconductor device structure of claim 10, wherein the first and second semiconductor layers comprise SiGe.

### Claim 12 (depends on 11)

The semiconductor device structure of claim 11, wherein the substrate portion comprises Si.

### Claim 13 (depends on 11)

The semiconductor device structure of claim 11, wherein first and second semiconductor layers each has a substantially uniform Ge concentration.

### Claim 14 (depends on 10)

The semiconductor device structure of claim 10, further comprising a gate electrode layer surrounding a portion of the first semiconductor layer, wherein the gate electrode layer is disposed over the second semiconductor layer.

### Claim 15 (depends on 14)

The semiconductor device structure of claim 14, further comprising a gate dielectric layer and an interfacial layer disposed between the first and second semiconductor layers, wherein the interfacial layer is in contact with the first and second semiconductor layers.

### Claim 16

A method for forming a semiconductor device structure, comprising:
forming a sacrificial gate structure over a first portion of a fin structure, wherein the fin structure comprises alternating first and second semiconductor layers;
recessing a second portion of the fin structure to expose a substrate portion;
removing the second semiconductor layers in a first region;
trimming the first semiconductor layers in the first region;
depositing a cap layer around the first semiconductor layers in the first region; and
forming first and second source/drain regions on opposite sides of the cap layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising replacing the second semiconductor layers with a dielectric material in a second region before removing the second semiconductor layers in the first region.

### Claim 18 (depends on 17)

The method of claim 17, further comprising depositing a mask layer in the second region, wherein the mask layer is formed on the first semiconductor layers and the dielectric material.

### Claim 19 (depends on 16)

The method of claim 16, further comprising depositing a mask layer in the second region before removing the second semiconductor layers in the first region, wherein the mask layer is formed on the first semiconductor layers and second semiconductor layers.

### Claim 20 (depends on 16)

The method of claim 16, further comprising performing an annealing process on the cap layer to form third semiconductor layers, wherein the third semiconductor layers and the first semiconductor layers comprise different materials.