# US 2026/0101563 A1 · Semiconductor device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101563 A1 - Document ID: US20260101563A1 - Status: Published application - Kind: A1 - Application number: 19/349,141 - Filed: 2025-10-03 - Published: 2026-04-09 - Earliest claimed: 2024-10-04 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Hideki OSADA; Tadashi YAMAGUCHI - Web page: https://patentgrep.com/patent/US20260101563A1 ## CPC - H10D 12/035: {Etching a recess in the emitter region (having a recessed gate H10D12/038)} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers} - H10D 64/01: Manufacture or treatment - H10D 64/0112: {using conductive layers comprising silicides} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/232: {Emitter electrodes for IGBTs} - H10P 14/412: {Deposition of metallic or metal-silicide materials} - H10W 20/033: {in openings in dielectrics} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10D 12/417: {having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region} - H10D 12/418: {having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes an insulating film, a metal film, and an adhesion intermediate film arranged between the insulating film and the metal film, and the adhesion intermediate film includes a first adhesion layer, a stress control layer, a second adhesion layer, and a barrier metal layer, which are mutually different and are arranged sequentially in a direction from the insulating film toward the metal film. The insulating film may contain silicon oxide. ## Claims ### Claim 1 A semiconductor device comprising: an insulating film; a metal film; and an adhesion intermediate film arranged between the insulating film and the metal film, wherein the adhesion intermediate film includes: a first adhesion layer; a stress control layer; a second adhesion layer; and a barrier metal layer, and wherein the first adhesion layer, the stress control layer, the second adhesion layer and the barrier metal layer are mutually different and are arranged sequentially in a direction from the insulating film toward the metal film. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the insulating film contains silicon oxide. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the metal film includes a stacked film in which a plurality of mutually different layers are stacked. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the metal film includes: a first metal layer containing tungsten arranged on the adhesion intermediate film; a second metal layer containing titanium arranged on the first metal layer; and a third metal layer containing aluminum arranged on the second metal layer. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the metal film includes: a second metal layer containing titanium arranged on the adhesion intermediate film; and a third metal layer containing aluminum arranged on the second metal layer. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the first adhesion layer, the stress control layer, and the second adhesion layer contain the same metal as one another, and wherein the same metal includes at least any of cobalt, nickel, molybdenum, hafnium, tantalum, tungsten, magnesium, chromium, manganese, iron, zirconium, niobium, rubidium, rhodium, palladium, rhenium, iridium, and platinum. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the first adhesion layer contains silicide. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein the first adhesion layer further contains silicon and oxygen. ### Claim 9 (depends on 6) The semiconductor device according to claim 6, wherein the stress control layer further contains at least any of halogens. ### Claim 10 (depends on 6) The semiconductor device according to claim 6, wherein the stress control layer further contains silicon, oxygen, and nitrogen. ### Claim 11 (depends on 6) The semiconductor device according to claim 6, wherein the second adhesion layer further contains oxygen and nitrogen. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein a thickness of the stress control layer is smaller than a thickness of the first adhesion layer. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein a thickness of the stress control layer is smaller than a thickness of the second adhesion layer. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, further comprising: a semiconductor substrate in which an IGBT is formed, the IGBT including a semiconductor layer including a drift layer, a channel layer, an emitter layer, and a collector layer, wherein the insulating film is formed on the semiconductor substrate, wherein the adhesion intermediate film is formed on the insulating film and on an inner wall of a contact hole penetrating from an upper surface of the insulating film to the semiconductor layer in the semiconductor substrate, and wherein the metal film is connected to the semiconductor layer via the adhesion intermediate film. ### Claim 15 A method of manufacturing a semiconductor device, the method comprising: forming an insulating film; forming an adhesion intermediate film on the insulating film; and forming a metal film on the adhesion intermediate film, wherein in forming the adhesion intermediate film, the adhesion intermediate film includes a first adhesion layer, a stress control layer, a second adhesion layer, and a barrier metal layer, and wherein the first adhesion layer, the stress control layer, the second adhesion layer, and the barrier metal layer are mutually different and are arranged sequentially in a direction from the insulating film toward the metal film. ### Claim 16 (depends on 15) The method according to claim 15, wherein forming the adhesion intermediate film includes: forming, on the insulating film, a halogenated metal film formed by halogenating a metal; transforming the halogenated metal film into a stacked transformation film including the first adhesion layer, the stress control layer, and the second adhesion layer, wherein the first adhesion layer, the stress control layer, and the second adhesion layer are mutually different and are arranged sequentially in a direction from the insulating film; and forming the barrier metal layer on the stacked transformation film. ### Claim 17 (depends on 16) The method according to claim 16, wherein transforming the halogenated metal film into the stacked transformation film includes: transforming the halogenated metal film into a pre-soak film including a first adhesion layer, a pre-stress control layer, and a pre-second adhesion layer, wherein the first adhesion layer, the pre-stress control layer, and the pre-second adhesion layer are mutually different and are arranged sequentially in a direction from the insulating film; and transforming the pre-soak film into the stacked transformation film including the first adhesion layer, the stress control layer, and the second adhesion layer, wherein the first adhesion layer, the stress control layer, and the second adhesion layer are mutually different and are arranged sequentially in a direction from the insulating film. ### Claim 18 (depends on 16) The method according to claim 16, wherein in transforming the halogenated metal film into the stacked transformation film, the halogenated metal film is transformed into the stacked transformation film by thermal process under an atmosphere containing ammonia. ### Claim 19 (depends on 16) The method according to claim 16, wherein in transforming the halogenated metal film into the stacked transformation film, the halogenated metal film is transformed into the stacked transformation film by thermal process under an atmosphere containing nitrogen and hydrogen. ### Claim 20 (depends on 15) The method according to claim 15, comprising: forming, in a semiconductor substrate, an IGBT including a semiconductor layer including a drift layer, a channel layer, an emitter layer, and a collector layer, wherein in forming the insulating film, the insulating film is formed on the semiconductor substrate, wherein in forming the adhesion intermediate film, the adhesion intermediate film is formed on the insulating film and on an inner wall of a contact hole penetrating from an upper surface of the insulating film toward the semiconductor layer in the semiconductor substrate, and wherein in forming the metal film, the metal film is connected to the semiconductor layer via the adhesion intermediate film.