# US 2026/0101550 A1 · Semiconductor devices with mixed channel

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2026/0101550 A1
- Document ID: US20260101550A1
- Status: Published application
- Kind: A1
- Application number: 18/907,691
- Filed: 2024-10-07
- Published: 2026-04-09
- Earliest claimed: 2024-10-07
- Assignees: Avago Technologies International Sales Pte. Limited
- Applicants: Avago Technologies International Sales Pte. Limited
- Inventors: Qing Liu
- Web page: https://patentgrep.com/patent/US20260101550A1

## CPC

- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)}
- H10D 62/8164: {comprising only semiconductor materials (potential variation in long-range structurally-disordered materials H10D62/8163)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device with a mixed channel that is suitable for operability under high operating voltages (e.g., 2.5 volts to 3.3 volts). The semiconductor device includes a drain; a source; a channel comprising a first nanosheet and a second nanosheet; sacrificial layer disposed between the first nanosheet and the second nanosheet; and a gate formed around the channel.

## Claims

### Claim 1

A semiconductor device, comprising:
a drain;
a source;
a channel comprising a first nanosheet and a second nanosheet;
a sacrificial layer disposed between the first nanosheet and the second nanosheet; and
a gate formed around the channel.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the first nanosheet and the second nanosheet consists of silicon; and
the sacrificial layer consists of silicon germanium.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the first nanosheet and the second nanosheet consist of silicon germanium having a first concentration of germanium;
the sacrificial layer consists of silicon germanium having a second concentration of germanium; and
the second concentration of germanium is greater than the first concentration of germanium.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein:
the first concentration of germanium is between 10 percent and 30 percent; and
the second concentration of germanium is between 35 percent and 65 percent.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein:
a thickness of the sacrificial layer measured in a direction between the first nanosheet and the second nanosheet is between 8 nanometers and 17 nanometers; and
a thickness of the first nanosheet measured in the direction between the first nanosheet and the second nanosheet is between 4 nanometers and 12 nanometers; and
a thickness of the second nanosheet measured in the direction between the first nanosheet and the second nanosheet is between 4 nanometers and 12 nanometers.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the sacrificial layer measured in a direction between the first nanosheet and the second nanosheet is greater than both a thickness of the first nanosheet measured in the direction between the first nanosheet and the second nanosheet and a thickness of the second nanosheet measured in the direction between the first nanosheet and the second nanosheet.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a length of the gate measured in a direction between the source and the drain is between 190 nanometers and 310 nanometers.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, comprising a trench disposed between the gate and the drain.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, comprising an isolation structure disposed under the trench, between the gate and the drain, and within a substrate of the semiconductor device.

### Claim 10

A semiconductor device, comprising:
a drain;
a source;
a channel comprising a first nanosheet, a second nanosheet, and a third nanosheet;
a first sacrificial layer disposed between the first nanosheet and the second nanosheet;
a second sacrificial layer disposed between the second nanosheet and the third nanosheet; and
a gate formed around the channel.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein:
the first nanosheet, the second nanosheet, and the third nanosheet consist of silicon; and
the sacrificial layer consists of silicon germanium.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein a ratio of a thickness of the first sacrificial layer measured in a direction between the first nanosheet and the second nanosheet is to a thickness of the first nanosheet measured in the direction between the first nanosheet and the second nanosheet is between 1.7 and 2.3.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein a length of the gate measured in a direction between the source and the drain is between 190 nanometers and 310 nanometers.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein:
the first nanosheet, the second nanosheet, and the third nanosheet consist of silicon germanium having a first concentration of germanium;
the first sacrificial layer and the second sacrificial layer consist of silicon germanium having a second concentration of germanium; and
the second concentration of germanium is greater than the first concentration of germanium.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, comprising:
a trench disposed between the gate and the drain; and
an isolation structure disposed under the trench, between the gate and the drain, and within a substrate of the semiconductor device.

### Claim 16

A circuit, comprising:
a substrate; and
a semiconductor device formed on the substrate, the semiconductor device comprising:
a drain;
a source;
a channel comprising a first nanosheet and a second nanosheet;
a sacrificial layer disposed between the first nanosheet and the second nanosheet; and
a gate formed around the channel.

### Claim 17 (depends on 16)

The circuit of claim 16, wherein:
the first nanosheet and the second nanosheet consists of silicon; and
the sacrificial layer consists of silicon germanium.

### Claim 18 (depends on 16)

The circuit of claim 16, wherein a thickness of the first sacrificial layer measured in a direction between the first nanosheet and the second nanosheet is greater than a thickness of the first nanosheet measured in the direction between the first nanosheet and the second nanosheet.

### Claim 19 (depends on 16)

The circuit of claim 16, wherein a length of the gate measured in a direction between the source and the drain is between 190 nanometers and 310 nanometers.

### Claim 20 (depends on 16)

The circuit of claim 16, wherein:
the first nanosheet and the second nanosheet consist of silicon germanium having a first concentration of germanium;
the sacrificial layer consists of silicon germanium having a second concentration of germanium; and
the second concentration of germanium is greater than the first concentration of germanium.