# US 2026/0101549 A1 · Placeholder for backside contact > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101549 A1 - Document ID: US20260101549A1 - Status: Published application - Kind: A1 - Application number: 18/910,315 - Filed: 2024-10-09 - Published: 2026-04-09 - Earliest claimed: 2024-10-09 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Lijuan Zou; Ruilong Xie; Tao Li; Fabio Carta; Erik Milosevic; Kisik Choi - Web page: https://patentgrep.com/patent/US20260101549A1 ## CPC - H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes} - H10D 30/506: {having different thicknesses, sizes or shapes} - H10D 30/6729: {characterised by the electrodes} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/251: {Source or drain electrodes for field-effect devices} - H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} - H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} - H10D 30/0194: {the stacked channels having different properties} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a transistor having a first and a second source/drain (S/D) region; a backside contact in contact with a bottom surface of the first S/D region; and a placeholder underneath the second S/D region, where the placeholder includes a first portion and a second portion on top of the first portion; the first portion being embedded in a backside interlevel-dielectric (BILD) layer; the second portion being at least partially surrounded by a dielectric liner; and a top section of the second portion being above the top surface of the BILD layer and surrounded by an airgap. ## Claims ### Claim 1 A semiconductor structure comprising: a transistor having a first and a second source/drain (S/D) region; a backside contact in contact with a bottom surface of the first S/D region; and a placeholder underneath the second S/D region, wherein the placeholder includes a first portion and a second portion on top of the first portion; the first portion being embedded in a backside interlevel-dielectric (BILD) layer; the second portion being at least partially surrounded by a dielectric liner; and a top surface of the second portion being above a top surface of the BILD layer. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein the second portion of the placeholder has an inverted trapezoidal shape with a wider base at top and a narrower base at bottom. ### Claim 3 (depends on 2) The semiconductor structure of claim 2, wherein a top section of the second portion of the placeholder is above the top surface of the BILD layer and is surrounded by an airgap, and a bottom section of the second portion of the placeholder is directly surrounded by the dielectric liner. ### Claim 4 (depends on 3) The semiconductor structure of claim 3, wherein a first portion of the backside contact directly contacts the first S/D region and is directly surrounded by the BILD layer. ### Claim 5 (depends on 2) The semiconductor structure of claim 2, wherein the second portion of the placeholder is directly surrounded by the dielectric liner and a top section of the second portion of the placeholder is surrounded by a set of inner spacers via the dielectric liner. ### Claim 6 (depends on 1) The semiconductor structure of claim 1, wherein the second portion of the placeholder has a top section in an inverted trapezoidal shape and a bottom section in a trapezoidal shape, both the top section and the bottom section being directly surrounded by the dielectric layer. ### Claim 7 (depends on 6) The semiconductor structure of claim 6, wherein the first portion of the placeholder and the bottom section of the second portion of the placeholder forms a diamond shape. ### Claim 8 (depends on 1) The semiconductor structure of claim 1, wherein the transistor is a nanosheet transistor having a set of nanosheets including a bottom-most nanosheet, and the top surface of the second portion of the placeholder is at or below the bottom-most nanosheet. ### Claim 9 A semiconductor structure comprising: a transistor having a first and a second source/drain (S/D) region; a backside contact in contact with a bottom surface of the first S/D region; and a placeholder underneath the second S/D region, wherein the placeholder includes a first portion and a second portion on top of the first portion, the first portion being embedded in a backside interlevel-dielectric (BILD) layer and the second portion being at least partially surrounded by a dielectric liner and a top surface of the second portion being above a top surface of the BILD layer. ### Claim 10 (depends on 9) The semiconductor structure of claim 9, wherein the second portion of the placeholder is directly surrounded by the dielectric liner and a top section of the second portion of the placeholder is further surrounded by a set of inner spacers via the dielectric liner, the set of inner spacers being above the top surface of the BILD layer. ### Claim 11 (depends on 10) The semiconductor structure of claim 10, wherein the dielectric liner is a first dielectric liner and a first portion of the backside contact directly contacts the first S/D region and is surrounded by a second dielectric liner, wherein the first dielectric liner and the second dielectric liner are made of a same dielectric material. ### Claim 12 (depends on 9) The semiconductor structure of claim 9, wherein the transistor is a nanosheet transistor having a set of nanosheets, and the top surface of the second portion of the placeholder is below the set of nanosheet. ### Claim 13 (depends on 9) The semiconductor structure of claim 9, wherein the second portion of the placeholder has a bottom section and a top section on top of the bottom section with both the bottom section and the top section being directly surrounded by the dielectric liner, a vertical cross-section of the top section having an inverted trapezoidal shape and a vertical cross-section of the bottom section having a trapezoidal shape. ### Claim 14 (depends on 13) The semiconductor structure of claim 13, wherein the first portion of the placeholder is directly surrounded by the BILD layer, the first portion of the placeholder and the bottom section of the second portion of the placeholder forms a diamond shape. ### Claim 15 (depends on 14) The semiconductor structure of claim 14, wherein the bottom section of the second portion of the placeholder is below the top surface of the BILD layer. ### Claim 16 A semiconductor structure comprising: a transistor having a first and a second source/drain (S/D) region; a backside contact in contact with a bottom surface of the first S/D region; and a placeholder underneath the second S/D region, wherein the placeholder includes a first portion and a second portion on top of the first portion, the first portion being embedded in a backside interlevel-dielectric (BILD) layer and the second portion being at least partially surrounded by a dielectric liner and a top surface of the second portion being above a top surface of the BILD layer. ### Claim 17 (depends on 16) The semiconductor structure of claim 16, wherein the placeholder is made of epitaxial silicon-germanium; the dielectric liner is made of silicon-nitride; and the BILD layer is made of silicon-oxide. ### Claim 18 (depends on 16) The semiconductor structure of claim 16, wherein the placeholder and the dielectric liner form an airgap surrounding a top section of the second portion of the placeholder. ### Claim 19 (depends on 18) The semiconductor structure of claim 18, wherein the transistor is a nanosheet transistor having a set of nanosheets, and wherein the airgap is below the set of nanosheets and above the BILD layer. ### Claim 20 (depends on 18) The semiconductor structure of claim 18, wherein a top section of the backside contact that directly contacts the first S/D region is surrounded by a set of inner spacers.