# US 2026/0101547 A1 · Two-step oxide trench silicon carbide mosfet

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- Number: US 2026/0101547 A1
- Document ID: US20260101547A1
- Status: Published application
- Kind: A1
- Application number: 18/909,424
- Filed: 2024-10-08
- Published: 2026-04-09
- Earliest claimed: 2024-10-08
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Meng Chia LEE; Dilip Madhav RISBUD
- Web page: https://patentgrep.com/patent/US20260101547A1

## CPC

- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 12/031: {of IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/8325: {Silicon carbide}
- H10D 64/01366: {the semiconductor being silicon carbide}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10P 30/22: using masks
- H10P 70/20: {Cleaning during device manufacture}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and processes for manufacturing semiconductors are described. A semiconductor device can include a drift region formed on a Silicon Carbide substrate. The semiconductor device can include a trench that penetrates through a source region and a channel and reaches the drift region. The semiconductor device can include an oxide region lining the trench. The oxide region can include a bottom portion, a lower side portion and an upper side portion. A thickness of the bottom portion and a thickness of the lower side portion can be greater than a thickness of the upper side portion. The semiconductor device can include a gate electrode formed in the trench lined with the oxide region. The semiconductor device can include a shield region in contact with a bottom portion of the trench. A width of the semiconductor region can be less than or equal to a width of the trench.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is formed by Silicon Carbide (SiC);
a drift region of the first conductivity type formed on the semiconductor substrate;
a channel of a second conductivity type opposite to the first conductivity type formed on the drift region;
a source region of the first conductivity type formed on the channel;
a trench that penetrates through the source region and the channel and reaches the drift region;
an oxide region that lines the trench, wherein:
the oxide region comprises a bottom portion, a lower side portion and an upper side portion;
a thickness of the bottom portion is greater than a thickness of the upper side portion; and
a thickness of the lower side portion is greater than the thickness of the upper side portion;
a gate electrode formed in the trench lined with the oxide region; and
a shield region of the second conductivity type in contact with the bottom portion of the trench and a width of the shield region is at most equal a width of the trench.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the lower side portion of the oxide region is in contact with the upper side portion of the oxide region.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the shield region is non-overlapping with a sidewall of the trench.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the drift region is in contact with at least a part of the upper side portion of the oxide region and at least a part of the lower side portion of the oxide region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein a thickness of the bottom portion of the oxide region is in a range of 1 nm to 500 nm.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a thickness of the lower side portion of the oxide region is in a range of 1 nm to 500 nm.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein an impurity concentration of the shield region is less than an impurity concentration of the channel.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein an impurity concentration of the shield region is in a range of 1×1015 cm−3 to 5×1017 cm−3.

### Claim 9

A semiconductor device comprising:
a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is formed by Silicon Carbide (SiC);
a drift region of the first conductivity type formed on the semiconductor substrate;
a channel of a second conductivity type opposite to the first conductivity type formed on the drift region;
a source region of the first conductivity type formed on the channel;
a trench that penetrates through the source region and the channel and reaches the drift region;
an oxide region that lines the trench, wherein:
the oxide region comprises a bottom portion, a lower side portion and an upper side portion;
a thickness of the bottom portion is greater than a thickness of the upper side portion; and
a thickness of the lower side portion is greater than the thickness of the upper side portion;
at least one gate electrode formed in the trench lined with the oxide region; and
a shield region of the second conductivity type in contact with the bottom portion of the trench and a width of the shield region is at most equal to a width of the trench.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the lower side portion of the oxide region is in contact with the upper side portion of the oxide region.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9, wherein the shield region is non-overlapping with a sidewall of the trench.

### Claim 12 (depends on 9)

The semiconductor device according to claim 9, wherein the drift region is in contact with at least a part of the upper side portion of the oxide region and at least a part of the lower side portion of the oxide region.

### Claim 13

A method of forming a semiconductor device, comprising:
forming a first oxide layer having a first thickness to line a trench formed in a Silicon Carbide (SiC) substrate;
forming a conductive material on a bottom portion of the trench lined with the first oxide layer;
forming a nitride layer above the conductive material and along sidewalls of the trench;
using the nitride layer as hardmask to etch the conductive material;
conducting a first oxidation process on a remaining portion of the conductive material to form a bottom portion and a lower side portion of an oxide region within the trench;
removing the nitride layer;
cleaning exposed sidewalls of the trench;
conducting a second oxidation process on the exposed sidewalls of the trench to form an upper side portion of the oxide region; and
forming a gate electrode in the trench lined with the oxide region.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming a shield region underneath the trench prior to forming the first oxide layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein a width of the shield region is less than or equal to a width of the trench.

### Claim 16 (depends on 14)

The method of claim 14, wherein the shield region is non-overlapping with a sidewall of the trench.

### Claim 17 (depends on 13)

The method of claim 13, wherein using the nitride layer as hardmask to etch the conductive material results in the remaining portion of the conductive material having a thickness similar to a thickness of the nitride layer.

### Claim 18 (depends on 13)

The method of claim 13, wherein:
the oxide region comprises the bottom portion, the lower side portion and the upper side portion;
a thickness of the bottom portion is greater than a thickness of the upper side portion; and
a thickness of the lower side portion is greater than the thickness of the upper side portion.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the thickness of the bottom portion is a combination of the first thickness and a thickness of a horizontal portion of the remaining portion of the conductive material;
the thickness of the lower side portion is the combination of the first thickness and a thickness of a vertical portion of the remaining portion of the conductive material; and
the thickness of the upper side portion is determined by a duration of the second oxidation process.

### Claim 20 (depends on 13)

The method of claim 13, further comprising:
forming a second oxide layer on the gate electrode;
forming another gate electrode on top of the second oxide layer; and
forming a passivation oxide layer on said another gate electrode.