# US 2026/0101533 A1 · Semiconductor Device

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- Number: US 2026/0101533 A1
- Document ID: US20260101533A1
- Status: Published application
- Kind: A1
- Application number: 19/417,002
- Filed: 2025-12-11
- Published: 2026-04-09
- Earliest claimed: 2020-02-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ze-Sian Lu; Ting-Wei Chiang; Pin-Dai Sue; Jung-Hsuan Chen; Hui-Wen Li
- Web page: https://patentgrep.com/patent/US20260101533A1

## CPC

- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 84/0193: {the components including FinFETs}
- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device includes: a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region. The first active region and the second active region are not fully projected in a vertical direction perpendicular to the substrate.

## Claims

### Claim at position 1

1-7. (canceled)

### Claim at position 2

9-17. (canceled)

### Claim 18

A method for forming a semiconductor device, comprising:
forming a first multi-gate field effect transistor (FET) disposed over a substrate, the first multi-gate FET including a first active region extending on a first horizontal plane; and
forming a second multi-gate FET disposed over the first multi-gate FET, the second multi-gate FET including a second active region extending on a second horizontal plane parallel to the first horizontal plane,
wherein the first active region and the second active region do not fully overlap when viewed from a vertical direction perpendicular to the first horizontal plane.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the first multi-gate FET includes a first metal contact region disposed over the first active region and a second metal contact region disposed over the first active region,
the second multi-gate FET further includes a third metal contact region disposed over the second active region and a fourth metal contact region disposed over the second active region, and
the first metal contact region and the third metal contact region do not fully overlap when viewed from the vertical direction, and the second metal contact region and the fourth metal contact region do not fully overlap when viewed from the vertical direction.

### Claim 20 (depends on 18)

The method of claim 18, wherein the first active region and the second active region have different conductivity types from each other.

### Claim 21 (depends on 18)

The method of claim 18, comprising forming a first projection of the second active region on the first horizontal plane partially overlapping with the first active region.

### Claim 22 (depends on 18)

The method of claim 18, comprising forming a first projection of the second active region on the first horizontal plane and not overlapping the first active region.

### Claim 23 (depends on 18)

The method of claim 18, comprising forming a first area of the first active region smaller than a second area of the second active region.

### Claim 24 (depends on 18)

The method of claim 18, comprising forming a first area of the first active region equal to a second area of the second active region.

### Claim 25 (depends on 18)

The method of claim 18, comprising forming a first area of the first active region larger than a second area of the second active region.

### Claim 26 (depends on 19)

The method of claim 19, comprising forming the second metal contact region and the third metal contact region to not fully overlap when viewed from the vertical direction.

### Claim 27 (depends on 18)

The method of claim 18, wherein forming the first multi-gate FET includes forming a first gate region adjacent to a plurality of side surfaces of the first active region, and forming the second multi-gate FET includes forming a second gate region adjacent to a plurality of side surfaces of the second active region.

### Claim 28 (depends on 27)

The method of claim 27, wherein the first gate region and the second gate region are separate.

### Claim 29 (depends on 27)

The method of claim 27, wherein the first gate region and the second gate region are connected.

### Claim 30 (depends on 18)

The method of claim 18, comprising forming a first width of the first active region equal to a second width of the second active region.

### Claim 31 (depends on 18)

The method of claim 18, comprising forming a first width of the first active region different from a second width of the second active region.

### Claim 32

A method for forming a semiconductor device, comprising:
forming a first multi-gate field effect transistor (FET) disposed over a substrate and including a first active region extending on a first horizontal plane; and
forming a second multi-gate FET disposed over the first multi-gate FET and including a second active region extending on a second horizontal plane parallel to the first horizontal plane, the first active region and the second active region not fully overlapping when viewed from a vertical direction perpendicular to the first horizontal plane,
wherein forming the first multi-gate FET includes forming a first metal contact region disposed over the first active region and a second metal contact region disposed over the first active region and forming the second multi-gate FET includes forming a third metal contact region disposed over the second active region and a fourth metal contact region disposed over the second active region, the first metal contact region and the third metal contact region not fully overlapping when viewed from a vertical direction, and the second metal contact region and the fourth metal contact region not fully overlapping when viewed from the vertical direction.

### Claim 33 (depends on 32)

The method of claim 32, comprising forming a first projection of the second active region on the first horizontal plane partially overlapping with the first active region.

### Claim 34 (depends on 32)

The method of claim 32, comprising forming a first projection of the second active region on the first horizontal plane and not overlapping the first active region.

### Claim 35

A method for forming a semiconductor device, comprising:
forming a first multi-gate field effect transistor (FET) disposed over a substrate and including a first active region extending on a first horizontal plane, a first metal contact region disposed over the first active region, and a second metal contact region disposed over the first active region; and
forming a second multi-gate FET disposed over the first multi-gate FET and including a second active region extending on a second horizontal plane parallel to the first horizontal plane, a third metal contact region disposed over the second active region, and a fourth metal contact region disposed over the second active region,
wherein the first active region and the second active region do not fully overlap when viewed from a vertical direction perpendicular to the first horizontal plane, the first metal contact region and the third metal contact region do not fully overlap when viewed from a vertical direction, and the second metal contact region and the fourth metal contact region do not fully overlap when viewed from the vertical direction.

### Claim 36 (depends on 35)

The method of claim 35, wherein the second metal contact region and the third metal contact region do not fully overlap when viewed from the vertical direction.

### Claim 37 (depends on 35)

The method of claim 35, wherein forming the first multi-gate FET includes forming a first gate region adjacent to a plurality of side surfaces of the first active region, and forming the second multi-gate FET includes forming a second gate region adjacent to a plurality of side surfaces of the second active region.