# US 2026/0101518 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101518 A1 - Document ID: US20260101518A1 - Status: Published application - Kind: A1 - Application number: 19/211,667 - Filed: 2025-05-19 - Published: 2026-04-09 - Earliest claimed: 2024-10-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Miso SHIN; Hansol KANG - Web page: https://patentgrep.com/patent/US20260101518A1 ## CPC - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 90/00: Package configurations - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads} - H10W 72/967: {Multiple bond pads having different functions} - H10W 90/792: {between multiple chips} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure relates to semiconductor devices, and semiconductor devices according to example embodiments include a first substrate structure and a second substrate structure on the first substrate structure, the first substrate structure including a first substrate including a cell area and a scribe lane area surrounding the cell area, first bonding pads over the cell area of the first substrate, and first dummy pads on the first substrate in the scribe lane area, the second substrate structure including a second substrate on the first substrate, and second bonding pads between the first substrate and the second substrate, joined with the plurality of first bonding pads, and a sum of the areas of the first dummy pads per a unit area in the scribe lane area is greater than or equal to a sum of the areas of the first bonding pads per a unit area in the cell area. ## Claims ### Claim 1 A semiconductor device comprising: a first substrate structure and a second substrate structure on the first substrate structure, the first substrate structure including a first substrate including a cell area and a scribe lane area surrounding the cell area, a plurality of first bonding pads over the cell area of the first substrate, and a plurality of first dummy pads on the first substrate in the scribe lane area, the second substrate structure including a second substrate on the first substrate, and a plurality of second bonding pads between the first substrate and the second substrate, and joined with the plurality of first bonding pads to each other, and a sum of the areas of the plurality of first dummy pads per a unit area in the scribe lane area is greater than or equal to a sum of the areas of the plurality of first bonding pads per a unit area in the cell area. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein: a diameter of the plurality of first bonding pads is smaller than a diameter of the plurality of first dummy pads. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein: a spacing between the plurality of first bonding pads is larger than a spacing between the plurality of first dummy pads. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein: a thickness of at least some of the plurality of first dummy pads is less than a thickness of the plurality of first bonding pads. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein: the second substrate structure further includes a plurality of second dummy pads between the first substrate and the second substrate and overlaps the plurality of first dummy pads. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein: a sum of the areas of the plurality of second dummy pads per a unit area is greater than or equal to a sum of the areas of the plurality of second bonding pads per a unit area. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein: the first substrate structure further includes a first junction insulation layer surrounding the plurality of first bonding pads and the plurality of first dummy pads, the second substrate structure further includes a second junction insulation layer surrounding the plurality of second bonding pads, and the first junction insulation layer is in contact with the second junction insulation layer. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein: the first junction insulation layer includes a recessed portion concave toward the first substrate in the scribe lane area. ### Claim 9 (depends on 7) The semiconductor device of claim 7, wherein: the first junction insulation layer and the second junction insulation layer include a same material, and the plurality of first bonding pads and the plurality of second bonding pads include a same material. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the first substrate structure further includes a lower wire above the first substrate in the cell area, a lower insulation layer between the lower wire and the plurality of first bonding pads, a first bonding via penetrating the lower insulation layer and connecting the plurality of first bonding pads and the lower wire, and the lower wire is electrically floating from the plurality of first dummy pads. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein: the first substrate structure further includes a first dummy via penetrating the lower insulation layer and connected to the plurality of first dummy pads, and the first dummy via includes a same material as each of the plurality of first dummy pads and is formed integrally. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein: the scribe lane area includes a first area apart from the cell area and including the plurality of first dummy pads, and a second area between the cell area and the first area and including the plurality of first dummy pads, the sum of the areas of the plurality of first dummy pads per a unit area in the second area is greater than the sum of the areas of the plurality of first bonding pads per a unit area in the cell area, and the sum of the areas of the plurality of first dummy pads per a unit area in the first area is greater than the sum of the areas of the plurality of first dummy pads per a unit area in the second area. ### Claim 13 (depends on 1) The semiconductor device of claim 1, wherein: the scribe lane area includes a key area separated from the cell area, and a first division area surrounding the key area and including the plurality of first dummy pads, and a second division area between the first division area and the cell area and including the plurality of first dummy pads, and the sum of the areas of the plurality of first dummy pads per a unit area in the first division area is greater than the sum of the areas of the plurality of first bonding pads per a unit area in the second division area. ### Claim 14 A semiconductor device comprising: a first substrate structure and a second substrate structure above the first substrate structure, the first substrate structure including a first substrate including a plurality of cell areas and a scribe lane area between the plurality of cell areas, a plurality of first bonding pads on the first substrate in the plurality of cell areas, a plurality of first dummy pads above the first substrate in the scribe lane area, and a first junction insulation layer surrounding the plurality of first bonding pads and the plurality of first dummy pads, the second substrate structure including a second substrate on the first substrate, a plurality of second bonding pads between the first substrate and the second substrate and joined with the plurality of first bonding pads each other, and a second junction insulation layer surrounding the plurality of second bonding pads and joined with at least a portion of an upper surface of the first junction insulation layer, and a sum of the areas of the plurality of first dummy pads per a unit area in the cell area is greater than or equal to a sum of the areas of the plurality of first bonding pads per a unit area. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the second substrate structure further includes a plurality of second dummy pads between the first substrate and the second substrate and overlapping the plurality of first dummy pads, and at least some of the plurality of second dummy pads are spaced in a vertical direction from the plurality of first dummy pads. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein a sum of the areas of the plurality of second dummy pads per a unit area is greater than or equal to a sum of the areas of the plurality of second bonding pads per a unit area. ### Claim 17 (depends on 15) The semiconductor device of claim 15, wherein a thickness of at least some of the plurality of first dummy pads is less than a thickness of the plurality of first bonding pads. ### Claim 18 (depends on 14) The semiconductor device of claim 14, wherein: the first junction insulation layer includes a same material as the second junction insulation layer, and the plurality of first bonding pads and the plurality of second bonding pads include the same material. ### Claim 19 A semiconductor device comprising: a first substrate structure and a second substrate structure above the first substrate structure, the first substrate structure including a first substrate including a cell area and a scribe lane area surrounding the cell area, a plurality of first bonding pads above the cell area of the first substrate, a plurality of first dummy pads above the scribe lane area of the first substrate, and a first junction insulation layer surrounding the plurality of first bonding pads and the plurality of first dummy pads, the second substrate structure including a second substrate on the first substrate, a plurality of second bonding pads between the first substrate and the second substrate and joined with the plurality of first bonding pads each other, and a second junction insulation layer surrounding a plurality of second bonding pads and junction with at least a portion of an upper surface of the first junction insulation layer in the cell area, the first junction insulation layer including a recessed portioned concave toward the first substrate in the scribe lane area, and a thickness of at least some of the plurality of first dummy pads is less than a thickness of the plurality of first bonding pads. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein at least a portion of the first junction insulation layer in the scribe lane area includes a portion spaced apart from the second junction insulation layer in a vertical direction.