# US 2026/0101501 A1 · Semiconductor memory device and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101501 A1 - Document ID: US20260101501A1 - Status: Published application - Kind: A1 - Application number: 19/211,014 - Filed: 2025-05-16 - Published: 2026-04-09 - Earliest claimed: 2024-10-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Soo Ho SHIN; Ji Hoon CHANG; Dong-Sik PARK - Web page: https://patentgrep.com/patent/US20260101501A1 ## CPC - H10B 12/485: {Bit line contacts} - H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug} - H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells} - H10B 12/315: {with the capacitor higher than a bit line} - H10B 12/34: {the transistor being at least partially in a trench in the substrate} - H10B 12/50: {Peripheral circuit region structures} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device includes a substrate including a first area and a second area arranged along a first direction, an active pattern disposed in the first area and including a first portion and a second portion, a gate electrode extending in a second direction intersecting the first direction, the gate electrode crossing between the first portion and the second portion, a conductive pattern disposed on the substrate and connected to the first portion, the conductive pattern extending in the first direction, and having an end on the second area, a buried contact disposed on a side surface of the conductive pattern on the first area to connect to the second portion, a capacitor structure connected to the buried contact, and an edge insulating film disposed on the side surface of the conductive pattern on the second area, the edge insulating film surrounding the end of the conductive pattern. ## Claims ### Claim 1 A semiconductor memory device comprising: a substrate including a first area and a second area arranged along a first direction; an active pattern disposed in the first area and including a first portion and a second portion; a gate electrode extending in a second direction intersecting the first direction, the gate electrode crossing between the first portion and the second portion; a conductive pattern disposed on the substrate and connected to the first portion, the conductive pattern extending in the first direction, and having an end on the second area; a buried contact disposed on a side surface of the conductive pattern on the first area, the buried contact connecting to the second portion; a capacitor structure connected to the buried contact; and an edge insulating film disposed on a side surface of the conductive pattern on the second area, the edge insulating film surrounding the end of the conductive pattern. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the edge insulating film comprises: a first filling portion overlapping the conductive pattern in the second direction; and a second filling portion overlapping the conductive pattern in the first direction. ### Claim 3 (depends on 2) The semiconductor memory device of claim 2, wherein the edge insulating film includes a seam extending in the first direction within the first filling portion and extending in the first direction within the second filing portion. ### Claim 4 (depends on 1) The semiconductor memory device of claim 1, further comprising: a fence insulating film overlapping the gate electrode in a third direction intersecting the upper surface of the substrate on the side surface of the conductive pattern on the first area. ### Claim 5 (depends on 4) The semiconductor memory device of claim 4, wherein the buried contact is interposed between the edge insulating film and the fence insulating film in the first direction. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, further comprising: a spacer structure disposed between the conductive pattern and the buried contact and between the conductive pattern and the edge insulating film and extending along the side surface of the conductive pattern. ### Claim 7 (depends on 6) The semiconductor memory device of claim 6, wherein a portion of the spacer structure is interposed between the substrate and the edge insulating film. ### Claim 8 (depends on 1) The semiconductor memory device of claim 1, further comprising: a landing pad disposed on an upper surface of the buried contact connecting the buried contact to the capacitor structure; and a dummy landing pad disposed on an upper surface of the edge insulating film and spaced apart from the landing pad. ### Claim 9 (depends on 1) The semiconductor memory device of claim 1, wherein the edge insulating film comprises a silicon nitride film. ### Claim 10 (depends on 1) The semiconductor memory device of claim 1, wherein the substrate comprises a gate trench extending in the second direction and crossing between the first portion and the second portion, wherein the gate electrode is buried in the gate trench. ### Claim 11 A semiconductor memory device comprising: a substrate including a first area and a second area arranged along a first direction; an active pattern disposed in the first area and including a first portion and a second portion; a gate electrode extending in a second direction intersecting the first direction, the gate electrode crossing between the first portion and the second portion; a conductive pattern disposed on the substrate and connected to the first portion, the conductive pattern extending in the first direction, and having an end on the second area; a spacer structure disposed on and extending along a side surface of the conductive pattern; a buried contact disposed on the spacer structure on the first area, the buried contact connecting to the second portion; a capacitor structure connected to the buried contact; and an edge insulating film disposed on the spacer structure on the second area, wherein a portion of the spacer structure is interposed between the substrate and the edge insulating film. ### Claim 12 (depends on 11) The semiconductor memory device of claim 11, wherein the edge insulating film comprises a seam spaced apart from the spacer structure. ### Claim 13 (depends on 11) The semiconductor memory device of claim 11, wherein the spacer structure comprises a first side spacer and a second side spacer sequentially stacked on the side surface of the conductive pattern, wherein a portion of the second side spacer extends along an upper surface of the substrate in the second area to be disposed between the substrate and the edge insulating film. ### Claim 14 (depends on 13) The semiconductor memory device of claim 13, wherein the buried contact extends through another portion of the second side spacer in the first area to connect to the second portion. ### Claim 15 (depends on 13) The semiconductor memory device of claim 13, wherein the first side spacer comprises a silicon oxide film, wherein the second side spacer includes a silicon nitride film. ### Claim 16 A semiconductor memory device comprising: a substrate including a cell area and a peripheral area around the cell area, wherein the cell area comprises a first area and a second area interposed between the first area and the peripheral area in a first direction; an active pattern disposed in the first area and including a first portion and a second portion; a gate electrode extending in a second direction intersecting the first direction, the gate electrode crossing between the first portion and the second portion; a first conductive line disposed on the substrate and connected to the first portion, the first conductive line extending in the first direction; a second conductive line disposed on the substrate and extending in the first direction, the second conductive line being spaced apart from the first conductive line in the second direction; a buried contact disposed between the first conductive line and the second conductive line and connecting the second portion; a capacitor structure connected to the buried contact; and an edge insulating film disposed on the second area, wherein the first conductive line comprises: a first line portion disposed on the first area; and a first edge portion disposed on the second area and having an end of the first conductive line, wherein the second conductive line comprises: a second line portion disposed on the first area; and a second edge portion disposed on the second area and having an end of the second conductive line, the second edge portion protruding beyond the first edge portion toward the peripheral area, wherein the edge insulating film comprises: a first filling portion interposed between the first edge portion and the second edge portion in the second direction; and a second filling portion overlapping the first edge portion in the first direction and overlapping the second edge portion in the second direction. ### Claim 17 (depends on 16) The semiconductor memory device of claim 16, wherein the edge insulating film comprises a seam extending in the first direction within the first filling portion, and extending in the first direction within the second filing portion. ### Claim 18 (depends on 16) The semiconductor memory device of claim 16, wherein the second edge portion comprises: an extension portion overlapping the first filling portion in the second direction; and an expansion portion overlapping the second filling portion in the second direction, wherein a width in the second direction of the expansion portion is larger than a width in the second direction of the extension portion. ### Claim 19 (depends on 18) The semiconductor memory device of claim 18, further comprising a contact plug in contact with the expansion portion. ### Claim 20 (depends on 16) The semiconductor memory device of claim 16, wherein the edge insulating film is an integral element.