# US 2026/0101484 A1 · Fan direction control using speed control signal for datacenter cooling systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101484 A1 - Document ID: US20260101484A1 - Status: Published application - Kind: A1 - Application number: 19/113,881 - Filed: 2022-09-23 - Published: 2026-04-09 - Earliest claimed: 2022-09-23 - Assignees: NVIDIA Corporation - Applicants: NVIDIA Corporation - Inventors: Pengwei Xu; Yongfa Gu - Web page: https://patentgrep.com/patent/US20260101484A1 ## CPC - H05K 7/20836: {Thermal management, e.g. server temperature control} - F04D 27/004: {by varying driving speed} - G05D 23/1917: {using digital means} - H05K 7/20745: {within rooms for removing heat from cabinets, e.g. by air conditioning device} - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - F04D: NON-POSITIVE-DISPLACEMENT PUMPS (engine fuel-injection pumps F02M; ion pumps H01J41/12; electrodynamic pumps H02K44/02) - G05D: SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES ## Abstract Systems and methods for cooling a datacenter (100) are disclosed. One or more circuits of a datacenter (100) cooling system can receive a speed control signal for a pulse width modulation (PWM) fan and can modify a speed control signal to output a direction control signal to a motor driver associated with a PWM fan, so that a direction control signal can enable a forward direction or a reverse direction for a PWM fan, while a speed control signal can enable a speed of a PWM fan. ## Claims ### Claim 1 A datacenter cooling system, comprising: one or more circuits to receive a speed control signal for a pulse width modulation (PWM) fan, to modify the speed control signal, and to output a direction control signal to a motor driver associated with the PWM fan, the direction control signal to enable a forward direction or a reverse direction for the PWM fan and the speed control signal to enable a speed of the PWM fan. ### Claim 2 (depends on 1) The datacenter cooling system of claim 1, further comprising: at least one processor to be associated with the one or more circuits and to provide an input to a controller, the controller to provide a PWM input signal that comprises the speed control signal to the one or more circuits to cause the one or more circuits to output the direction control signal for one of the forward direction or the reverse direction for the PWM fan. ### Claim 3 (depends on 1) The datacenter cooling system of claim 1, further comprising: a buffer circuit of the one or more circuits, the buffer circuit to receive a PWM input signal that comprises the speed control signal and to enable an adjustment to the PWM input signal. ### Claim 4 (depends on 3) The datacenter cooling system of claim 3, wherein the adjustment is to change a frequency or a duty cycle of the PWM input signal. ### Claim 5 (depends on 3) The datacenter cooling system of claim 3, further comprising: an RC low pass filter of the one or more circuits to receive a buffer output signal of the buffer circuit and to filter the buffer output signal to a buffer output direct current (DC) voltage signal that is expressed in part as a product of a buffer supply voltage and a duty cycle of the PWM input signal. ### Claim 6 (depends on 5) The datacenter cooling system of claim 5, further comprising: a comparator of the one or more circuits to compare voltages of the buffer output DC voltage signal and a preset voltage signal, wherein a preset voltage of the preset voltage signal is expressed in part as a product of the buffer supply voltage and a threshold duty cycle and wherein the preset voltage is less than a product of the buffer supply voltage and a minimum duty cycle required to startup the PWM fan. ### Claim 7 (depends on 5) The datacenter cooling system of claim 5, further comprising: a comparator of the one or more circuits to compare the buffer output DC voltage signal and a preset voltage signal that is expressed in part as a product of the buffer supply voltage and a threshold duty cycle, wherein a comparator output signal comprises a first voltage and a second voltage at different times, wherein the first voltage is lower than the second voltage, wherein the first voltage is comprised in the comparator output signal for a buffer output DC voltage of the buffer output DC voltage signal that is greater than a preset voltage of the preset voltage signal, and wherein the second voltage is comprised in the comparator output signal for the buffer output DC voltage that is lesser than a preset voltage of the preset voltage signal. ### Claim 8 (depends on 7) The datacenter cooling system of claim 7, further comprising: a positive-edge-triggered D-type flip-flop of the one or more circuits to receive the comparator output signal in a clock pin, wherein a preset pin and a clear pin of the positive-edge-triggered D-type flip-flop are to be provided with predetermined voltages at a power-on phase and at an operational phase of the PWM fan. ### Claim 9 (depends on 8) The datacenter cooling system of claim 8, wherein, during the power-on phase, the preset pin is to be set to a third voltage that is higher relative to a first rated voltage for the positive-edge-triggered D-type flip-flop and wherein the clear pin is set to have a change in voltage relative to a second rated voltage for the positive-edge-triggered D-type flip-flop. ### Claim 10 (depends on 8) The datacenter cooling system of claim 8, wherein, during the operational phase, the preset pin and the clear pin are both set to a third voltage that is higher relative to a first rated voltage for the positive-edge-triggered D-type flip-flop. ### Claim 11 (depends on 1) The datacenter cooling system of claim 1, further comprising: one or more neural networks to receive a sensor input associated with a sensor that is adapted to provide the sensor input upon a performance change of the PWM fan or adapted to provide the sensor input upon a blockage in airflow through a heatsink associated with the PWM fan, the one or more neural networks to infer a value associated with the performance change or the blockage in the airflow, the one or more neural networks trained using prior sensor inputs and prior values of performance changes or blockages in the airflow, the inference to enable the one or more circuits to cause the forward direction or the reverse direction for the PWM fan. ### Claim 12 A processor comprising one or more circuits within a datacenter cooling system, the processor to receive a sensor input from a sensor in a datacenter and to enable the one or more circuits to receive a speed control signal for a pulse width modulation (PWM) fan, the one or more circuits further to modify the speed control signal and to output a direction control signal to a motor driver associated with the PWM fan, the direction control signal to enable a forward direction or a reverse direction for the PWM fan and the speed control signal to enable a speed of the PWM fan. ### Claim 13 (depends on 12) The processor of claim 12, further comprising: an output of the processor to provide the speed control signal to the one or more circuits or to enable a controller to provide the speed control signals to the one or more circuits. ### Claim 14 (depends on 12) The processor of claim 12, further comprising: an input of the processor to receive the sensor input from the sensor, the processor to determine a requirement to change a direction of the PWM fan from the sensor inputs. ### Claim 15 (depends on 14) The processor of claim 14, further comprising: one or more neural networks to receive the sensor input and to infer the requirement to change the direction of the PWM fan. ### Claim 16 A method for a datacenter cooling system, comprising: providing one or more circuits to receive a speed control signal for a pulse width modulation (PWM) fan; modifying the speed control signal to provide a direction control signal; outputting the direction control signal to a motor driver associated with the PWM fan; and enabling a forward direction or a reverse direction for the PWM fan based in part on the direction control signal and enabling a speed for the PWM fan based in part on the speed control signal. ### Claim 17 (depends on 16) The method of claim 16, further comprising: providing, using at least one processor associated with the one or more circuits, an input to a controller; providing, by the controller, a PWM input signal that comprises the speed control signal to the one or more circuits; and outputting to a motor driver, by the one or more circuits, the direction control signal for one of the forward direction or the reverse direction for the PWM fan. ### Claim 18 (depends on 16) The method of claim 16, further comprising: receiving, in one or more neural networks, a sensor input associated with a sensor that is adapted to provide the sensor input upon a performance change of the PWM fan or adapted to provide the sensor input upon a blockage in airflow through a heatsink associated with the PWM fan; inferring, by the one or more neural networks, a value associated with the performance change or the blockage in the airflow, the one or more neural networks trained using prior sensor inputs and prior values of performance changes or blockages in the airflow; and enabling, by the inference of the one or more neural networks, the one or more circuits to cause the forward direction or the reverse direction for the PWM fan. ### Claim 19 (depends on 16) The method of claim 16, further comprising: adjusting, by a buffer circuit of the one or more circuits, a PWM input signal that comprises the speed control signal, to provide a buffer output signal; filtering, by an RC low pass filter of the one or more circuits, the buffer output signal to provide a buffer output direct current (DC) voltage signal that is expressed in part as a product of a buffer supply voltage and a duty cycle of the PWM input signal; and comparing, by a comparator of the one or more circuits, the buffer output DC voltage signal and a preset voltage signal that is expressed in part as a product of the buffer supply voltage and a PWM threshold duty cycle to provide a comparator output signal that comprises a first voltage and a second voltage at different times, the first voltage lower than the second voltage, wherein the first voltage is comprised in the comparator output signal for a buffer output DC voltage of the buffer output DC voltage signal that is greater than a preset voltage of the preset voltage signal, and wherein the second voltage is comprised in the comparator output signal for the buffer output DC voltage that is lesser than a preset voltage of the preset voltage signal. ### Claim 20 (depends on 19) The method of claim 19, further comprising: providing, by a positive-edge-triggered D-type flip-flop of the one or more circuits, the direction control signal upon receipt of the comparator output signal in a clock pin, wherein a preset pin and a clear pin of the positive-edge-triggered D-type flip-flop are to be provided with predetermined voltages at a power-on phase and at an operational phase of the PWM fan.