Rtc micro-second counter

A wireless receiver comprising a low-power timing circuit, the low-power timing circuit configured to:

• calculate a Timing Synchronization Function (TSF) value for a current cycle using a low-frequency clock source,
• calculate an error for the current cycle,
• compare the error for the current cycle to a previous error,
• calculate a residual error if the error for the current cycle is less than the previous error,
• determine correction parameters if the residual error is non-zero, and
• apply periodic corrections to the TSF value based on the correction parameters.

A circuit for implementing a Timing Synchronization Function (TSF) counter, the circuit comprising:

• a first multiplexer with multiple input lines for different increment values;
• an adder coupled to the first multiplexer;
• a TSF counter register coupled to the adder;
• a last-second value register coupled to the TSF counter register;
• a second multiplexer coupled to the TSF counter register and the last-second value register;
• and
• a control logic circuit coupled to the first multiplexer, the second multiplexer, and the TSF counter register.