# US 2026/0101281 A1 · Iterative detection and decoding (idd) circuit for calculating low-power consumption log-likelihood ratio, operation method of the idd circuit, and modem chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101281 A1 - Document ID: US20260101281A1 - Status: Published application - Kind: A1 - Application number: 19/239,332 - Filed: 2025-06-16 - Published: 2026-04-09 - Earliest claimed: 2024-10-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Joohan KIM; Jangho LEE; Youngseok JUNG - Web page: https://patentgrep.com/patent/US20260101281A1 ## CPC - H04W 52/0209: {in terminal devices} - H04B 7/0413: MIMO systems - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) - H04B: TRANSMISSION ## Abstract Provided are an iterative detection and decoding (IDD) circuit, which includes a multiple-input and multiple-output (MIMO) detector having low power consumption, an operation method of the IDD circuit, and a modem chip. The IDD circuit, which is configured to receive a signal including a symbol, includes a first detector configured to generate a first log-likelihood ratio based on the symbol by using a linear detection method, a decoding circuit configured to perform a first decoding operation based on the first log-likelihood ratio and to generate a post-log-likelihood ratio when the first decoding operation fails, and a second detector configured to, when the first decoding operation fails, generate a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method, wherein the decoding circuit is further configured to perform a second decoding operation based on the second log-likelihood ratio. ## Claims ### Claim 1 An iterative detection and decoding (IDD) circuit configured to receive a signal including a symbol, the IDD circuit comprising: a first detector configured to generate a first log-likelihood ratio based on the symbol by using a linear detection method; a decoding circuit configured to perform a first decoding operation based on the first log-likelihood ratio and to generate a post-log-likelihood ratio when the first decoding operation fails; and a second detector configured to, when the first decoding operation fails, generate a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method, wherein the decoding circuit is further configured to perform a second decoding operation based on the second log-likelihood ratio. ### Claim 2 (depends on 1) The IDD circuit of claim 1, wherein the IDD circuit is further configured to perform N iterative operations, where N is an integer of 2 or more, a first iterative operation from among the N iterative operations comprises a first detection operation for generating the first log-likelihood ratio by the first detector and the first decoding operation, and a last iterative operation from among the N iterative operations comprises a second detection operation for generating the second log-likelihood ratio by the second detector and the second decoding operation. ### Claim 3 (depends on 1) The IDD circuit of claim 1, wherein the decoding circuit comprises: a first circuit configured to generate a pre-log-likelihood ratio by performing a de-interleaving operation and a rate de-matching operation based on at least one of the first log-likelihood ratio and the second log-likelihood ratio; a second circuit configured to generate a third log-likelihood ratio by performing an interleaving operation and a rate matching operation based on the post-log-likelihood ratio; and a soft-input and soft-output (SISO) decoder configured to perform at least one of the first decoding operation and the second decoding operation based on the pre-log-likelihood ratio. ### Claim 4 (depends on 1) The IDD circuit of claim 1, wherein the decoding circuit is further configured to perform a cyclic redundancy check (CRC) operation, and to determine that a failure of the CRC operation indicates a failure of the first decoding operation. ### Claim 5 (depends on 1) The IDD circuit of claim 1, wherein the linear detection method comprises a method of generating the first log-likelihood ratio by using a linear detection matrix that comprises at least one of a minimum mean square error (MMSE) weight matrix, a zero forcing (ZF) weight matrix, and a QR decomposition (QRD) weight matrix. ### Claim 6 (depends on 1) The IDD circuit of claim 1, wherein the nonlinear detection method comprises a method of generating the second log-likelihood ratio by using at least one of a maximum likelihood (ML) algorithm and a near-ML algorithm. ### Claim 7 (depends on 6) The IDD circuit of claim 6, wherein the second detector is further configured to generate the second log-likelihood ratio based on the first log-likelihood ratio and the post-log-likelihood ratio, when the nonlinear detection method comprises a method of generating the second log-likelihood ratio by using the near-ML algorithm. ### Claim 8 (depends on 1) The IDD circuit of claim 1, wherein the nonlinear detection method comprises a method of searching for an initial point, selecting K candidates based on the initial point, and generating the second log-likelihood ratio based on at least one of Euclidean distances between the K candidates and the initial point, where K is a positive integer. ### Claim 9 (depends on 8) The IDD circuit of claim 8, wherein the initial point is searched for by using the first detector. ### Claim 10 An operation method of an iterative detection and decoding (IDD) circuit, the operation method comprising: receiving a signal including a symbol; and performing N iterative operations, where N is an integer of 2 or more, wherein a first iterative operation from among the N iterative operations comprises: generating a first log-likelihood ratio based on the symbol by using a linear detection method; performing a first decoding operation based on the first log-likelihood ratio; terminating the N iterative operations, when the first decoding operation is successful; and generating a post-log-likelihood ratio based on the first log-likelihood ratio, when the first decoding operation fails, and an N-th iterative operation from among the N iterative operations comprises: generating a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method; and performing a second decoding operation based on the second log-likelihood ratio. ### Claim 11 (depends on 10) The operation method of claim 10, wherein the performing of the first decoding operation further comprises: performing a cyclic redundancy check (CRC) operation; and determining that a failure of the CRC operation indicates a failure of the first decoding operation. ### Claim 12 (depends on 10) The operation method of claim 10, wherein the linear detection method comprises a method of generating the first log-likelihood ratio by using a linear detection matrix that comprises at least one of a minimum mean square error (MMSE) weight matrix, a zero forcing (ZF) weight matrix, and a QR decomposition (QRD) weight matrix. ### Claim 13 (depends on 10) The operation method of claim 10, wherein the nonlinear detection method comprises a method of generating the second log-likelihood ratio by using at least one of a maximum likelihood (ML) algorithm and a near-ML algorithm. ### Claim 14 (depends on 10) The operation method of claim 10, wherein the generating of the second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using the nonlinear detection method comprises: searching for an initial point; selecting K candidates based on the initial point, where K is a positive integer; and generating the second log-likelihood ratio based on at least one of Euclidean distances between the K candidates and the initial point. ### Claim 15 (depends on 14) The operation method of claim 14, wherein the searching for of the initial point comprises searching for the initial point based on the linear detection method. ### Claim 16 A modem chip comprising: a radio-frequency integrated circuit (RFIC); and a processor configured to receive, via the RFIC, a reception signal including a symbol, wherein the processor is further configured to: generate a first log-likelihood ratio based on the symbol by using a linear detection method; perform a first decoding operation based on the first log-likelihood ratio; generate a post-log-likelihood ratio, when the first decoding operation fails; generate a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method, when the first decoding operation fails; and perform a second decoding operation based on the second log-likelihood ratio. ### Claim 17 (depends on 16) The modem chip of claim 16, wherein the processor is further configured to perform N iterative operations, where N is an integer of 2 or more, a first iterative operation from among the N iterative operations comprises a first detection operation for generating the first log-likelihood ratio and the first decoding operation, and an N-th iterative operation from among the N iterative operations comprises a second detection operation for generating the second log-likelihood ratio and the second decoding operation. ### Claim 18 (depends on 16) The modem chip of claim 16, wherein the linear detection method comprises a method of generating the first log-likelihood ratio by using a linear detection matrix that comprises at least one of a minimum mean square error (MMSE) weight matrix, a zero forcing (ZF) weight matrix, and a QR decomposition (QRD) weight matrix. ### Claim 19 (depends on 16) The modem chip of claim 16, wherein the nonlinear detection method comprises a method of searching for an initial point, selecting K candidates based on the initial point, and generating the second log-likelihood ratio based on at least one of Euclidean distances between the K candidates and the initial point, where K is a positive integer. ### Claim 20 (depends on 19) The modem chip of claim 19, wherein the initial point is searched for based on a first detection operation for generating the first log-likelihood ratio.