# US 2026/0101059 A1 · Memory latency management for decoder-side motion refinement > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0101059 A1 - Document ID: US20260101059A1 - Status: Published application - Kind: A1 - Application number: 19/207,161 - Filed: 2025-05-13 - Published: 2026-04-09 - Earliest claimed: 2018-06-22 - Assignees: Avago Technologies International Sales Pte. Limited - Applicants: Avago Technologies International Sales Pte. Ltd. - Inventors: Minhua ZHOU - Web page: https://patentgrep.com/patent/US20260101059A1 ## CPC - H04N 19/513: Processing of motion vectors - H04N 19/119: Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks - H04N 19/137: Motion inside a coding unit, e.g. average field, frame or block difference - H04N 19/423: characterised by memory arrangements (H04N19/433 takes precedence) - H04N 19/43: Hardware specially adapted for motion estimation or compensation - H04N 19/88: involving rearrangement of data among different coding units, e.g. shuffling, interleaving, scrambling or permutation of pixel data or permutation of transform coefficient data among different blocks - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A system includes memory and at least one processor coupled to the memory. The processor processes a received bitstream to generate quantized data and control data. The process also generates decoded motion data based on a portion of the control data, fetches one or more reference blocks associated with a current prediction unit of a decoder pipeline region based on the decoded motion data and generates refined motion data based on the decoded motion data and the one or more reference blocks. The processor further generates one or more inter-prediction blocks based on the refined motion data and the one or more reference blocks by performing a motion compensation operation. ## Claims ### Claim 1 A system comprising: memory; and at least one processor coupled to the memory and configured to: process a received bitstream to generate quantized data and control data; generate decoded motion data based on a portion of the control data; fetch one or more reference blocks associated with a current prediction unit (PU) of a decoder pipeline region (DPR) based on the decoded motion data; generate refined motion data based on the decoded motion data and the one or more reference blocks; and generate one or more inter-prediction blocks based on the refined motion data and the one or more reference blocks by performing a motion compensation operation. ### Claim 2 (depends on 1) The system of claim 1, wherein the processor is configured to generate the decoded motion data by performing a motion-data reconstruction operation. ### Claim 3 (depends on 2) The system of claim 2, wherein the processor is configured to generate refined motion data by using a decoder-side motion estimation (DME) operation that excludes feedback of the refined motion data to the motion-data reconstruction operation. ### Claim 4 (depends on 1) The system of claim 1, wherein the processor is further configured to generate the one or more inter-prediction blocks prior to generating the refined motion data. ### Claim 5 (depends on 1) The system of claim 1, wherein the control data comprises inter-prediction parameters and intra-prediction parameters, and the portion of the control data comprises inter-prediction parameters including motion vector differences (MVDs) and merge indices. ### Claim 6 A pipeline video decoder comprising: an engine configured to receive a bitstream and to convert the bitstream into symbol data including pixel data and control parameters; a coarse-motion reconstruction block configured to generate decoder-pipeline region (DPR)-based coarse motion data based on a portion of the control parameters; a direct memory accesses (DMA) block configured to fetch reference data associated with a current prediction unit (PU) of a DPR based on the coarse motion data; and a motion-vector predictor configured to generate decoded motion data based on the portion of the control parameters and feedback refined motion data, wherein the feedback refined motion data is generated by a decoder-side motion estimation (DME) block based on the decoded motion data and the reference data. ### Claim 7 (depends on 6) The pipeline video decoder of claim 6, wherein the motion-vector predictor is configured to generate the decoded motion data by interleaving a motion-data reconstruction with the feedback refined motion data at a coding unit (CU) level, and wherein generating the decoded motion data is decoupled from fetching the one or more reference blocks. ### Claim 8 (depends on 6) The pipeline video decoder of claim 6, wherein the portion of the control parameters comprise inter-prediction parameters including motion vector differences (MVDs) and merge indices. ### Claim 9 (depends on 6) The pipeline video decoder of claim 6, wherein the decoded motion data comprises an initial motion vector, and wherein the DME block is configured to perform a DME operation around the initial motion vector to generate the feedback refined motion data. ### Claim 10 (depends on 9) The pipeline video decoder of claim 9, wherein the reference data comprises a reference block, and wherein the DMA block is configured to fetch the reference block for the current PU around a coarse motion vector by extending a displaced PU corresponding to the current PU in four directions. ### Claim 11 (depends on 9) The pipeline video decoder of claim 9, Further comprising a motion compensation (MC) block, and wherein the DME block and the MC block are configured to access reference samples outside a pre-fetched reference block by performing reference pixel padding. ### Claim 12 (depends on 9) The pipeline video decoder of claim 9, wherein in a reference pixel padding a nearest reference-block boundary sample is used for operations of the DME block and the MC block. ### Claim 13 A method comprising: receiving, by an engine, a bitstream; converting, by the engine the bitstream into symbol data including pixel data and control parameters; generating decoder-pipeline region (DPR)-based coarse motion data based on a portion of the control parameters; fetching reference data associated with a current prediction unit (PU) of a DPR based on the coarse motion data; and generating decoded motion data based on the portion of the control parameters and feedback refined motion data based on the decoded motion data and the reference data. ### Claim 14 (depends on 13) The method of claim 13, further comprising generating the decoded motion data by interleaving a motion-data reconstruction with the feedback refined motion data at a coding unit (CU) level. ### Claim 15 (depends on 14) The method of claim 14, wherein generating the decoded motion data is decoupled from fetching the one or more reference blocks. ### Claim 16 (depends on 14) The method of claim 14, wherein the portion of the control parameters comprise inter-prediction parameters including motion vector differences (MVDs) and merge indices. ### Claim 17 (depends on 14) The method of claim 14, wherein the decoded motion data comprises an initial motion vector, and wherein the method further comprises performing a decoder-side motion estimation (DME) operation around the initial motion vector to generate the feedback refined motion data. ### Claim 18 (depends on 17) The method of claim 17, wherein the reference data comprises a reference block, and wherein the method further comprises fetching the reference block for the current PU around a coarse motion vector by extending a displaced PU corresponding to the current PU in four directions. ### Claim 19 (depends on 17) The method of claim 17, further comprising accessing reference samples outside a pre-fetched reference block by performing reference pixel padding. ### Claim 20 (depends on 17) The method of claim 17, further comprising using, in a reference pixel padding, a nearest reference-block boundary sample for operations of a DME block and a motion compensation (MC) block.