Decoder circuit, corresponding receiver and transmission system

A receiver, comprising:

• a demodulator configured to:
• receive a frequency shift keying (FSK) modulated signal modulated over an FSK carrier;
• and
• produce, from the FSK modulated signal, a sequence of demodulated symbols having level transitions between adjacent demodulated symbols and at least part of the demodulated symbols having level transitions between adjacent signaling elements therein;
• and
• a decoder coupled to the demodulator, and comprising:
• a sample counter configured to sample the sequence of demodulated symbols in response to a count of the sample counter reaching a sampling point value;
• a comparator coupled with the sample counter, wherein the comparator is configured to perform a comparison with at least one reference threshold of samples from the sequence of demodulated symbols sampled by the sample counter in response to the count of the sample counter reaching the sampling point value;
• a buffer circuit configured to store results of the comparison for at least three adjacent signaling elements of the demodulated symbols;
• and
• logic circuitry coupled to the buffer circuit and configured to:
• detect, based on the results of the comparison for the at least three adjacent signaling elements for subsequent and consecutive demodulated symbols over a reference period of time, an isolated absence or a persisting absence of the level transitions;
• and
• assert an error-in-transmission signal in response to the isolated absence of the level transitions detected over the reference period of time;
• or
• assert an end-of-transmission signal in response to the persisting absence of the level transitions detected over the reference period of time.

A communication system comprising:

• a transmitter configured to transmit a modulated signal wherein a carrier is modulated via modulation symbols having level transitions between adjacent modulation symbols and at least part of the modulation symbols having level transitions between adjacent signaling elements therein;
• and
• a receiver, comprising:
• a demodulator configured to:
• receive the modulated signal;
• and
• produce, from the modulated signal, a sequence of demodulated symbols having level transitions between adjacent demodulated symbols and at least part of the demodulated symbols having level transitions between adjacent signaling elements therein;
• and
• a decoder coupled to the demodulator, and comprising:
• a sample counter configured to sample the sequence of demodulated symbols in response to a count of the sample counter reaching a sampling point value;
• a comparator coupled with the sample counter, wherein the comparator is configured to perform a comparison with at least one reference threshold of samples from the sequence of demodulated symbols sampled by the sample counter in response to the count of the sample counter reaching the sampling point value;
• a buffer circuit configured to store results of the comparison for at least three adjacent signaling elements of the demodulated symbols;
• and
• logic circuitry coupled to the buffer circuit and configured to:
• detect, based on the results of the comparison for the at least three adjacent signaling elements for subsequent and consecutive demodulated symbols over a reference period of time, an isolated absence or a persisting absence of the level transitions;
• and
• assert an error-in-transmission signal in response to the isolated absence of the level transitions detected over the reference period of time;
• or
• assert an end-of-transmission signal in response to the persisting absence of the level transitions detected over the reference period of time.