Jitter correction in a receiver device

A receiver device comprising:

• a first equalizer block to obtain current data based on an incoming signal sampled by an analog-to-digital converter (ADC);
• and
• a jitter correction circuit coupled to the first equalizer block, the jitter correction circuit comprising:
• an estimator block to determine an average phase-offset value over a specified time by multiplying a measurement of an instantaneous phase offset during a number of clock cycles by a first parameter value;
• a gain control block to determine a sign of the average phase-offset value and select either a first gain value or a second gain value based on the sign, the first gain value and the second gain value being different;
• a phase detector gain block to determine a phase-offset value based on the average phase-offset value and the first gain value or the second gain value selected by the gain control block;
• a delay block to delay the current data to align the current data with the phase-offset value corresponding to the current data;
• and
• a re-sample block to re-sample the current data using the phase-offset value to obtain re-sampled data to reduce jitter in the current data.

A method comprising:

• generating samples of an incoming signal using an analog-to-digital converter (ADC);
• determining current data from the samples using an equalizer block;
• measuring, using a timing error detector (TED) of a clock recovery (CR) block, a sampling offset of the current data to control sampling of subsequent data by the ADC;
• determining an average phase-offset value over a specified time by multiplying a measurement of an instantaneous sampling offset during a number of clock cycles by a first parameter value;
• determining a sign of the average phase-offset value and selecting either a first gain value or a second gain value based on the sign, the first gain value and the second gain value being different;
• determining a phase-offset value based on the average phase-offset value and the first gain value or the second gain value selected;
• and
• re-sampling the current data using the phase-offset value to obtain re-sampled data to reduce jitter in the current data.

A system for high-speed network communication, the system comprising:

• a processing unit;
• and
• a network interface coupled to the processing unit, wherein the network interface comprises a receiver device, wherein the receiver device comprises:
• an analog-to-digital converter (ADC) to sample an incoming signal to obtain samples;
• and
• a signal processing circuit coupled to the ADC, wherein the signal processing circuit comprises an equalizer block, a phase detector block, and a jitter correction block, wherein the jitter correction block is to:
• receive current data from the equalizer block;
• determine a running sum value based on phase information received from the phase detector block;
• apply either a first gain value or a second gain value to the running sum value to obtain a phase correction value based on a sign of the running sum value, wherein the first gain value and the second gain value are different;
• and
• re-sample, using the phase correction value, the current data to obtain re-sampled data to reduce jitter in the current data.