US 2026/0100730 A1 · SIGNAL GENERATION IN AND/OR FOR RADIO

Abstract

A method includes generating an output clock in a digitally controlled oscillator, dividing the output clock to generate a divided clock, generating a feedback clock based on the divided clock, generating an error signal based on a phase difference between a reference clock and the feedback clock, and controlling the digitally controlled oscillator based on the error signal, wherein generating the feedback clock includes connecting a first current source to a capacitor according to a fixed delay with respect to the divided clock, connecting a second current source to the capacitor prior to the fixed delay according to a first programmable select parameter, connecting a third current source to the capacitor prior to the fixed delay according to a second programmable select parameter, and generating the feedback clock based on a voltage of the capacitor after connecting the first, second, and third current sources to the capacitor.

Claims20

Dependent claims

A method, comprising:

generating an output clock signal in a digitally controlled oscillator;
dividing the output clock signal to generate a divided clock signal;
generating a feedback clock signal based on the divided clock signal;
generating a phase error signal based on a phase difference between a reference clock signal and the feedback clock signal;
and
controlling the digitally controlled oscillator based on the phase error signal, wherein:
generating the feedback clock signal comprises:
connecting a first current source to a capacitor according to a fixed delay with respect to the divided clock signal;
connecting a second current source to the capacitor prior to the fixed delay according to a first programmable select parameter;
connecting a third current source to the capacitor prior to the fixed delay according to a second programmable select parameter;
and
generating the feedback clock signal based on a voltage of the capacitor after connecting the first current source, the second current source, and the third current source to the capacitor.

9 more elements

A frequency synthesizer, comprising:

a digitally controlled oscillator configured to generate an output clock signal based on a digital control word;
a clock divider configured to divide the output clock signal to generate a divided clock signal;
a digital-to-time converter configured to generate a feedback clock signal based on the divided clock signal;
a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal;
and
a loop filter configured to generate the digital control word based on the phase error signal, wherein:
the digital-to-time converter comprises:
a delay circuit, comprising:
a capacitor;
a first current source;
a second current source;
a third current source;
and
a buffer configured to generate the feedback clock signal based on a voltage of the capacitor;
and
a precharge generator configured to:
generate a first timing signal for connecting the first current source to the capacitor according to a fixed delay with respect to the divided clock signal;
generate a second timing signal for connecting the second current source to the capacitor according to a first programmable select parameter;
and
generate a third timing signal for connecting the third current source to the capacitor according to a second programmable select parameter.

17 more elements

A radio, comprising:

an antenna port;
a transmit-receive switch connected to the antenna port;
a receive path connected to the transmit-receive switch;
a transmit path connected to the transmit-receive switch;
and
a processor configured to connect the receive path to the transmit-receive switch in a receive mode of the radio and connect the transmit path to the transmit-receive switch in a transmit mode of the radio, wherein:
the transmit path comprises:
a frequency synthesizer configured to generate an output clock signal;
a local oscillator generator configured to generate a local oscillator signal based on the output clock signal;
and
a power amplifier connected to the transmit-receive switch and configured to amplify the local oscillator signal to generate a transmit signal;
the frequency synthesizer comprises:
a digitally controlled oscillator configured to generate the output clock signal based on a digital control word;
a clock divider configured to divide the output clock signal to generate a divided clock signal;
a digital-to-time converter configured to generate a feedback clock signal based on the divided clock signal;
a time-to-digital converter configured to generate a phase error signal based on a bias control word and a phase difference between a reference clock signal and the feedback clock signal;
and
a loop filter connected to the time-to-digital converter and configured to generate the digital control word based on the phase error signal, wherein:
the digital-to-time converter comprises:
a delay circuit, comprising:
a capacitor;
a first current source;
a second current source;
a third current source;
and
a buffer configured to generate the feedback clock signal based on a voltage of the capacitor;
and
a precharge generator configured to:
generate a first timing signal for connecting the first current source to the capacitor according to a fixed delay with respect to the divided clock signal;
generate a second timing signal for connecting the second current source to the capacitor according to a first programmable select parameter;
and
generate a third timing signal for connecting the third current source to the capacitor according to a second programmable select parameter.

29 more elements

Dependencies are inferred from the claim text.

Signal generation in and/or for radio

Life of this patent

Signal generation in and/or for radio

Life of this patent

Abstract

Claims20