US 2026/0100712 A1 · DELAY LOCKED LOOP DEVICE AND METHOD FOR OPERATING THE SAME

Abstract

A delay locked loop device is provided, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal. The delay line delays the first signal to generate a second signal based on a delay control signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate an enable signal. The phase detector detects, in response to the enable signal, a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit is configured to generate the delay control signal for the delay line based on the phase detection result.

Claims20

Dependent claims

A delay locked loop device, comprising:

a receiver, configured to compare an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal;
a delay line, configured to delay the first signal to generate a second signal based on a delay control signal;
a frequency detection and control circuit, configured to detect an operating frequency of the reference clock signal to generate an enable signal;
a phase detector, configured to detect, in response to the enable signal in a high logic state, a phase difference between the reference clock signal and a feedback clock signal, which is generated from the second signal, to generate a phase detection result;
and
a delay control circuit, configured to generate the delay control signal for the delay line based on the phase detection result.

3 more elements

A delay locked loop device, comprising:

a receiver, configured to compare an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal;
a delay line, configured to delay the first signal to generate a second signal based on a delay control signal;
a frequency detection and control circuit, configured to detect an operating frequency of the reference clock signal to generate a divider selection signal;
a first clock divider, configured to divide, based on the divider selection signal, the reference clock signal using a specific cycle count among a plurality of cycle counts to generate a divided reference clock signal;
a second clock divider, configured to divide, based on the divider selection signal, a feedback clock signal generated from the second signal to generate a divided feedback clock signal;
a phase detector, configured to detect a phase difference between the divided reference clock signal and the divided feedback clock signal to generate a phase detection result;
and
a delay control circuit, configured to generate the delay control signal for the delay line based on the phase detection result.

5 more elements

Dependencies are inferred from the claim text.

Delay locked loop device and method for operating the same

Life of this patent

Delay locked loop device and method for operating the same

Life of this patent

Abstract

Claims20