Duty cycle correction of phase interpolator output

A phase interpolator in an integrated circuit (IC), comprising:

• a first current source and a second current source;
• a first transistor pair including a first transistor coupled between a first node and the first current source, and a second transistor coupled between a second node and the first current source, the first transistor pair configured to output a first clock signal at the first node and a second clock signal at the second node, the second clock signal being antiphase with the first clock signal;
• a second transistor pair including a third transistor coupled between a third node and the second current source, and a fourth transistor coupled between a fourth node and the second current source, the second transistor pair configured to output a third clock signal, which is in quadrature with the first clock signal, at the third node and a fourth clock signal at the fourth node, the fourth clock signal being antiphase with the third clock signal;
• a first inductor coupled between the first and second nodes and a second inductor coupled between the third and fourth nodes;
• a first resistor coupled between a voltage source a center terminal of the first inductor and a second resistor coupled between the voltage source and a center terminal of the second inductor;
• a first network coupled between the center terminal of the first inductor and an alternating current (AC) ground;
• and
• a second network coupled between the center terminal of the second inductor and the AC ground.

A clock distribution circuit in an integrated circuit (IC), comprising:

• a phase interpolator comprising:
• a first circuit including a transistor pair and a current source, the transistor pair including a first transistor coupled between a first node and the current source, and second transistor coupled between a second node and the current source, a gate of the first transistor configured to receive a first clock signal and a gate of the second transistor configured to receive a second clock signal that is antiphase with the first clock signal;
• a load circuit including a first inductor coupled between the first node and the second node and a first resistor coupled between a voltage source and a center terminal of the first inductor;
• and
• a second circuit coupled between the center terminal of the first inductor and an alternating current (AC) ground, the second circuit tuned to conduct a second harmonic of the first clock signal;
• a third circuit coupled to the first node, the third circuit including a first series of inverters, a second resistor coupled between an input and an output of a first inverter in the first series;
• and
• a fourth circuit coupled to the second node, the fourth circuit including a second series of inverters, a third resistor coupled between an input and an output of a second inverter in the second series.