# US 2026/0100698 A1 · Dynamic high-speed flip flop > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0100698 A1 - Document ID: US20260100698A1 - Status: Published application - Kind: A1 - Application number: 18/908,295 - Filed: 2024-10-07 - Published: 2026-04-09 - Earliest claimed: 2024-10-07 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Peter Normand LABRECQUE; Anik SRIVASTAVA; Sumeer GOEL - Web page: https://patentgrep.com/patent/US20260100698A1 ## CPC - H03K 3/013: Modifications of generator to prevent operation by noise or interference - H03K 3/35625: {using complementary field-effect transistors} - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Aspects of the disclosure are directed to a dynamic master slave flip flop circuit. In accordance with one aspect, the disclosure includes a master latch section configured to receive an input signal asserted at a HIGH state of the input signal; a clock circuit coupled to the master latch section, the clock circuit configured to execute a positive clock transition of a clock signal; and a slave latch section coupled to the master latch section and the clock circuit, the slave latch section configured to transition a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition. ## Claims ### Claim 1 An apparatus comprising: a master latch section configured to receive an input signal asserted at a HIGH state of the input signal; a clock circuit coupled to the master latch section, the clock circuit configured to execute a positive clock transition of a clock signal; and a slave latch section coupled to the master latch section and the clock circuit, the slave latch section configured to transition a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising a first slave latch transistor configured to implement a glitch mitigation in the slave latch section. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the first slave latch transistor is housed within the slave latch section. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the first slave latch transistor is a metal oxide semiconductor (MOS) transistor. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the metal oxide semiconductor (MOS) transistor is an n-channel MOS (NMOS) transistor. ### Claim 6 (depends on 5) The apparatus of claim 5, further comprising a second slave latch transistor housed within the slave latch section, the second slave latch transistor configured to gate the positive clock transition. ### Claim 7 An apparatus comprising: means for receiving an input signal asserted at a HIGH state of the input signal at a master latch section, and at a slave latch section with a glitch mitigation; means for executing a positive clock transition throughout the master latch section and the slave latch section; and means for transitioning a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition. ### Claim 8 (depends on 7) The apparatus of claim 7, further comprising means for transitioning a complementary state (QB) signal from a first state to a second state subsequent to the positive clock transition. ### Claim 9 (depends on 8) The apparatus of claim 8, further comprising means for receiving the input signal deasserted at a LOW state. ### Claim 10 (depends on 9) The apparatus of claim 9, further comprising means for inputting the input signal. ### Claim 11 A method comprising: receiving an input signal asserted at a HIGH state of the input signal at a master latch section, and at a slave latch section with a glitch mitigation; executing a positive clock transition throughout the master latch section and the slave latch section; and transitioning a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition. ### Claim 12 (depends on 11) The method of claim 11, wherein the positive clock transition is gated in a keeper circuit. ### Claim 13 (depends on 11) The method of claim 11, wherein the positive clock transition is a rising edge of a periodic clock signal. ### Claim 14 (depends on 13) The method of claim 13, wherein the periodic clock signal is established using a frequency reference. ### Claim 15 (depends on 11) The method of claim 11, further comprising transitioning a complementary state (QB) signal from a first state to a second state subsequent to the positive clock transition. ### Claim 16 (depends on 15) The method of claim 15, wherein the complementary state (QB) signal tracks a complement of the input signal with a first delay. ### Claim 17 (depends on 16) The method of claim 16, wherein the state (Q) signal tracks the input signal with a second delay. ### Claim 18 (depends on 15) The method of claim 15, further comprising receiving the input signal deasserted at a LOW state at the master latch section, and at the slave latch section with the glitch mitigation. ### Claim 19 (depends on 18) The method of claim 18, further comprising inputting the input signal to the master latch section and to the slave latch section. ### Claim 20 (depends on 18) The method of claim 18, wherein the input signal is received prior to a setup time margin relative to the positive clock transition.