# US 2026/0100237 A1 · Memory device and operation method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0100237 A1 - Document ID: US20260100237A1 - Status: Published application - Kind: A1 - Application number: 19/266,755 - Filed: 2025-07-11 - Published: 2026-04-09 - Earliest claimed: 2024-10-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Taeyun Lee - Web page: https://patentgrep.com/patent/US20260100237A1 ## CPC - G11C 29/12005: {comprising voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/1201: {comprising I/O circuitry} - G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits - G11C 2029/1802: {Address decoder} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a memory block with a plurality of cell strings connected to a bit line, each of the cell strings including a plurality of selection transistors connected to a plurality of selection lines and a plurality of memory cells connected to a plurality of word lines, a row decoding circuit that applies at least two different test voltages to the plurality of selection lines and applies pass voltages to the word lines, in a test operation, and a control circuit including a sensing node. In the test operation, the control circuit connects the bit line and the sensing node during a first time after the test voltages are applied, to sense whether a voltage of the sensing node is changed to a first reference voltage or lower, and terminates the test operation or performs a subsequent operation following the test operation, based on the sensing. ## Claims ### Claim 1 A memory device comprising: a memory block including a plurality of cell strings connected to a bit line, wherein each of the plurality of cell strings includes a plurality of selection transistors connected to a plurality of selection lines, and a plurality of memory cells connected to a plurality of word lines; a row decoding circuit configured to apply at least two different first test voltages to the plurality of selection lines and to apply pass voltages to the word lines, in a test operation; and a control circuit including a sensing node, wherein, in the test operation, the control circuit is configured to connect the bit line and the sensing node during a first time after the at least two different first test voltages are applied, to sense whether a voltage of the sensing node is changed to a first reference voltage or lower; and terminate the test operation or perform a subsequent operation following the test operation, based on sensing whether the voltage of the sensing node is changed to the first reference voltage or lower. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the at least two different first test voltages are different from each other depending on a threshold voltage range in which the plurality of selection transistors are programmed. ### Claim 3 (depends on 1) The memory device of claim 1, wherein, based on the voltage of the sensing node exceeding the first reference voltage during the first time, the control circuit is configured to check, as the subsequent operation, a threshold voltage range of the plurality of selection transistors. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the first time is shorter than a second time, wherein the control circuit is configured to sense a voltage change of the sensing node in a read or verify operation during the second time. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the first reference voltage is lower than a second reference voltage, wherein the control circuit is configured to sense a voltage change of the sensing node in a read or verify operation based on the second reference voltage. ### Claim 6 (depends on 1) The memory device of claim 1, wherein, in the test operation, a capacitance of the sensing node connected to the bit line is configured to be a first capacitance, and wherein, in a read or verify operation, the capacitance of the sensing node connected to the bit line is configured to be a second capacitance that is smaller than the first capacitance. ### Claim 7 (depends on 1) The memory device of claim 1, wherein a page buffer circuit is configured to apply a first precharge voltage to the sensing node in the test operation, and to apply a second precharge voltage to the sensing node in a read or verify operation, wherein the first precharge voltage is higher than the second precharge voltage. ### Claim 8 (depends on 1) The memory device of claim 1, wherein each of the plurality of cell strings further includes a plurality of dummy memory cells connected to a plurality of dummy word lines, and wherein, in the test operation, the row decoding circuit is configured to apply at least two different second test voltages to the dummy word lines. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the plurality of cell strings are connected between the bit line and a common source line, wherein the plurality of selection transistors includes a plurality of ground selection transistors connected to a plurality of ground selection lines, and wherein, based on application of a selection voltage to the at least one ground selection line, at least one of ground selection transistor connected to at least one ground selection line from among the plurality of ground selection transistors is configured to be turned on, and at least another ground selection line is configured to be turned off. ### Claim 10 An operation method of a memory device, the memory device comprising a sensing node, a bit line, a first cell string, and a second cell string connected to the bit line, the first cell string comprising first selection transistors and first memory cells and the second cell string comprising second selection transistors and second memory cells, the method comprising: precharging the bit line and the sensing node; applying at least two different test voltages to the first selection transistors and the second selection transistors; applying pass voltages to the first memory cells and the second memory cells; connecting the sensing node and the bit line to sense whether a voltage of the sensing node is changed to a first reference voltage or lower during a first time; and performing a subsequent operation for the memory device, based on the sensing. ### Claim 11 (depends on 10) The method of claim 10, wherein, in a first test mode, applying the at least two different test voltages includes: applying the at least two different test voltages to the first selection transistors; and applying shut-off voltages to at least one of the second selection transistors. ### Claim 12 (depends on 11) The method of claim 11, wherein performing the subsequent operation comprises performing a test operation for each of the first selection transistors in response to the voltage of the sensing node exceeding the first reference voltage during the first time. ### Claim 13 (depends on 11) The method of claim 11, wherein the first time is shorter than a second time, the method comprising sensing a voltage change of the sensing node in a read or verify operation during the second time. ### Claim 14 (depends on 10) The method of claim 10, wherein, in a second test mode, applying at least two different test voltages comprises: performing a test operation for a first transistor among the first selection transistors and for a second transistor among the second selection transistors; and applying the pass voltages to remaining transistors among the first and second selection transistors. ### Claim 15 (depends on 14) The method of claim 14, wherein the first time is longer than a second time, the method comprising sensing a voltage change of the sensing node in a read or verify operation during the second time. ### Claim 16 (depends on 10) The method of claim 10, wherein the first selection transistors and the second selection transistors comprise dummy memory cells. ### Claim 17 A storage device comprising: a nonvolatile memory device including a plurality of memory blocks and a control circuit controlling the plurality of memory blocks; and a memory controller configured to control the nonvolatile memory device, wherein each of the plurality of memory blocks includes a plurality of cell strings, wherein each of the plurality of cell strings includes a plurality of selection transistors connected to a plurality of selection lines and a plurality of memory cells connected to a plurality of word lines, and wherein the control circuit is configured to: apply at least two different test voltages to selection lines connected to a first cell string included in a first memory block among the plurality of memory blocks; and apply pass voltages to word lines connected to the first cell string to check whether a channel path of the first cell string is formed. ### Claim 18 (depends on 17) The storage device of claim 17, wherein the memory controller includes a bad block manage circuit configured to treat the first memory block as a bad memory block, based on the channel path of the first cell string being formed. ### Claim 19 (depends on 17) The storage device of claim 17, wherein the memory controller includes a re-program control circuit configured to re-program threshold voltages of the selection transistors included in the first cell string, based on the channel path of the first cell string being formed. ### Claim 20 (depends on 19) The storage device of claim 19, wherein the re-program control circuit is configured to migrate valid data of the first memory block to a second memory block and to then perform an erase operation for the first memory block.